UVM Error : These constraints contribute to the set of conflicting constraints

[Khushi]

With the following code,

import uvm_pkg::*;
`include "uvm_macros.svh"

class seq_data extends uvm_sequence_item;
    `uvm_object_utils(seq_data)
    rand bit [7:0] addr;
    rand bit [7:0] data;

    constraint c_addr {addr >=1000;addr<2000;}
    constraint c_data {data >=0000;data<=4000;}

    function new (string name = "",uvm_component parent=null);
        super.new(name);
    endfunction

    virtual function void display ();
         `uvm_info (get_type_name (), $sformatf ("addr = 0x%0h, data = 0x%0h", addr, data), UVM_LOW);
    endfunction
endclass

class my_test extends uvm_test;
    `uvm_component_utils(my_test)

    seq_data my_data;

   function new(string name, uvm_component parent);
     super.new(name, parent);
   endfunction

   function void build_phase(uvm_phase phase);
       my_data = seq_data::type_id::create("my_data",this);
   endfunction

   task run_phase(uvm_phase phase);
      phase.raise_objection(this);
      repeat(4) begin
         #10;
         assert(my_data.randomize());
         my_data.display();
      end
      phase.drop_objection(this);
   endtask

  endclass

module top;
initial begin
    run_test("my_test");
  end
endmodule 

 

I am getting the following error

xmsim: *E,ASRTST (./example.sv,38): (time 30 NS) Assertion worklib.$unit_0x762d41ec::my_test::run_phase.__assert_1 has failed
UVM_INFO example.sv(17) @ 30: reporter@@my_data [seq_data] addr = 0x0, data = 0x0
         assert(my_data.randomize());
                                |
xmsim: *W,SVRNDF (./example.sv,38|32): The randomize method call failed. The unique id of the failed randomize call is 3.
Observed simulation time : 40 NS + 0
xmsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints:

    constraint c_addr {addr >=1000;addr<2000;} (./example.sv,9)
xmsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints:

rand variables:
       addr [./example.sv, 6]

 

I am not seeing any constraint with the following expression

    constraint c_addr {addr >=1000;addr<2000;} (./example.sv,9)

Can someone help me to understand what is going wrong here ?

Thanks

Khushi

 

 

[mastrick]

The problem is that your example code has the constraint block c_addr with "addr>=1000" but addr is an 8-bit field and so could not hold a value of 1000 or greater.

[Khushi]

Thanks Mastrick.