Khushi Posted July 24, 2018 Report Share Posted July 24, 2018 Hi Guys I am trying to use uvm_reg_hw_reset_seq built in sequence but it seems it generates all address (e.g. 0x0,0x1,0x2,0x3,0x4,...) but as the registers are 32 bit, I expect 0x0,0x4,0x8 etc How I can control this ? Thanks Quote Link to comment Share on other sites More sharing options...
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