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Found 6 results

  1. Hi, I have declared and defined the clock in my example and able to generate and transport the transactions successfullly. As its is a blocking transport interface of tlm,so we are using wait statement. But what i observed here is, i am not able to control the triggering of process by using clocks for both the modules.Thiugh , i am able to controll the thread awakening by using delay statements. What if i want to use clocks to controll the trigger ,thats why i had put them in the sensitivity list. Please let me know,what would be my approach for the triggering by clocks.? do i need to look out for other interface method in tlm or should i go back to system c interface approach ? Please help me out with this. Thanks & regards, Shubham Ps:- I am attaching the code along with the block diagram below,please let me know the solution for it.The block diagram represents 2 blocks of initiator and target modules with clock supplied. Iam able to compile and run the code succesfully,if you get any error while compiling i might have done mistake while copying. initiator.h.txt main.cpp.txt target.h.txt initiator2.h.txt target2.h.txt top.h.txt
  2. Hello Guys I have a scenario where I have an initiator module on SystemC side and target module on UVL side. From initiator side, I call b_transport with some payload and in target side the data field is modified. What I am seeing that when b_transport returns on initiator module, the changes in data field is not reflected. On SystemC side, I have a thread with following function void run(){ int i = 4; while(i--){ cout<<" in run........"<<endl; tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload; sc_time delay = sc_time(100, SC_NS); trans->set_command(tlm::TLM_WRITE_COMMAND); uint64_t addr = 0x0; uint8_t data = 0xa5; uint32_t length = 1; trans->set_address(addr); trans->set_data_ptr( reinterpret_cast<unsigned char*>(&data)); trans->set_data_length(length); trans->set_streaming_width(length); trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); initiator_socket->b_transport(*trans,delay); cout<<"Result : 0xa5 vs 0x"<<hex<<+data<<endl; wait(delay); } } On UVM target side, my b_transport implementation is as follows task b_transport(uvm_tlm_generic_payload gp, uvm_tlm_time delay); byte unsigned data[]; gp.get_data(data); `uvm_info("INFO", $sformatf("entering b_transport with data[0] : 0x%x",gp.m_data[0]), UVM_LOW); data[0] = ~data[0]; gp.set_data(data); `uvm_info("INFO", $sformatf("exiting b_transport with data[0] : 0x%x",gp.m_data[0]), UVM_LOW); endtask and the output I am getting is UVM_INFO @ 0: reporter [RNTST] Running test SV:sv_top set by +UVM_TESTNAME... in run........ UVM_INFO sv_target.sv(31) @ 0: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 0: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 in run........ UVM_INFO sv_target.sv(31) @ 100000: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 100000: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 in run........ UVM_INFO sv_target.sv(31) @ 200000: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 200000: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 in run........ UVM_INFO sv_target.sv(31) @ 300000: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 300000: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 It seems that on UVM side the data field is updated well but on TLM side it is not reflected. Can you help me to understand what is going wrong here ? Thanks Khushi
  3. Hello, I've scoured the internet and this forum for what I imagine will have a very simple solution. Apparently I am not describing it sufficiently. I have a SystemC model comprised of a handful of registers, and single memory bank. I would like to implement TWO blocking transport interfaces to this model. If I implement a single blocking transport ( via inheritance of b_transport ), the method has access to all the model resources. If I want two b_transport interfaces, I've had to move them to channels, which are then instantiated in the model. These channels do not have access to the model resources of course, because they are declared seperately from the model. They communicate transactions to the model via an event (or using a fifo). Therefore, the blocking transport will issue a wait(sc_zero_time) for the transaction to reach the model and perform some action. *Perhaps this solution is already what I should be doing. However, I like the idea of a blocking transport actually setting the value and returning (with no wait statements); but, I cannot do this because I need TWO of these methods. Brian
  4. Hello, I'm trying to compile a design with a TLM2 socket (simple_initiator_socket) in ModelSim (sccom). So far, the compiler returns an error saying that there is no function called b_transport. Yet I have this same design working in the PoC SC simulator, so I'm guessing that ModelSim is doing things differently than the PoC. However ModelSim does point out an alternative, which was to use blocking_transport_if's version. I believe this was the one used all along in the PoC, and it should be the same in ModelSim. Any ideas? Here are the designs: Initiator /** * RTL-to-TLM2 Adaptor */ ... /** Includes **/ ... #include <tlm.h> #include <tlm_utils/simple_initiator_socket.h> ... struct rtl_to_tlm2_adaptor: public sc_channel { /** TLM-2 simple initiator socket **/ tlm_utils::simple_initiator_socket<rtl_to_tlm2_adaptor> rtt2a_socket; ... /** Adaptor constructor **/ SC_HAS_PROCESS( rtl_to_tlm2_adaptor ); rtl_to_tlm2_adaptor(sc_module_name _name) : sc_module(_name), addr(0), data(0), cmd(tlm::TLM_IGNORE_COMMAND) { // Construct and name socket SC_THREAD(write_thread); // Register adaptor channel thread SC_THREAD(read_thread); // Register read/write method trans = new tlm::tlm_generic_payload; // Create new payload instance } private: ... // Variables defined here /** Methods **/ // Sets up TLM2 payload void payload_setup(tlm::tlm_generic_payload* trans, tlm::tlm_command cmd, signed short& data, uint64 addr) { // Initialize 8 out of the 10 TLM-2 attributes, byte_enable_length and extensions being unused trans->set_command(cmd); trans->set_address(addr); trans->set_data_ptr(reinterpret_cast<unsigned char*>(&data)); trans->set_data_length(MEM_DATA_WORD_LEN); trans->set_streaming_width(MEM_DATA_WORD_LEN); trans->set_byte_enable_ptr(0); trans->set_dmi_allowed(false); trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); } // Local b_transport used to execute the standard TLM2 procedures void local_b_transport() { payload_setup(trans, cmd, data, addr); // Payload setup rtt2a_socket->b_transport(*trans, sc_time(SC_ZERO_TIME)); // Blocking transport call // Initiator obliged to check response status and delay if (trans->is_response_error()) SC_REPORT_ERROR("TLM-2", "Response error from b_transport"); } // Memory write procedure void mem_write() { cmd = tlm::TLM_WRITE_COMMAND; // Set command ... local_b_transport(); // Call local b_transport ... } // Memory read procedure void mem_read() { cmd = tlm::TLM_READ_COMMAND; // Set command ... local_b_transport(); // Call local b_transport ... } }; #endif Target /** * Generic memory instance, mostly inspired by Doulos' example */ ... /** Includes **/ #include <tlm.h> #include <tlm_utils/simple_target_socket.h> ... struct gen_mem: sc_module { /** TLM-2 simple target socket **/ tlm_utils::simple_target_socket<gen_mem> mem_socket; /** Generic memory constructor **/ SC_CTOR(gen_mem) : mem_socket("mem_socket") { // Register callback for incoming b_transport interface method call mem_socket.register_b_transport(this, &gen_mem::b_transport); dont_initialize(); // Mark to not initialize thread // Initialize memory with random data mem_reset(); } // TLM-2 blocking transport method virtual void b_transport(tlm::tlm_generic_payload& trans, sc_time& delay) { tlm::tlm_command cmd = trans.get_command(); // Get command sc_dt::uint64 adr = trans.get_address(); // Get address unsigned char* ptr = trans.get_data_ptr(); // Get data pointer unsigned int len = trans.get_data_length(); // Get data length unsigned char* byt = trans.get_byte_enable_ptr(); // Get byte enable pointer unsigned int wid = trans.get_streaming_width(); // Get streaming width // Obliged to check address range and check for unsupported features if (adr >= sc_dt::uint64(MEM_SIZE) || byt != 0 || len > 16 || wid < len) SC_REPORT_ERROR("TLM-2", "Target does not support given generic payload transaction"); // Obliged to implement read and write commands if (cmd == tlm::TLM_READ_COMMAND) { // Read command memcpy(ptr, &mem[adr], len); // Use memcopy function to copy memory address pointer // cout << sc_time_stamp() << " MEMORY: Reading value " << *(mem+adr) << " @" << adr << endl; } else if (cmd == tlm::TLM_WRITE_COMMAND) { // Write command memcpy(&mem[adr], ptr, len); // Use memcopy function to copy to memory // cout << sc_time_stamp() << " MEMORY: Writing value " << *ptr << " @" << adr << endl; } else if (cmd == tlm::TLM_IGNORE_COMMAND) { // Reset command mem_reset(); // Reset memory // cout << sc_time_stamp() << " MEMORY: Reset requested" << endl; } else SC_REPORT_ERROR("TLM-2", "Command not supported"); // Obliged to set response status to indicate successful completion trans.set_response_status(tlm::TLM_OK_RESPONSE); // Realize wait delay to advance simulation time wait(delay); } private: unsigned short mem[MEM_SIZE]; // Memory array instance void mem_reset() { for (int i = 0; i < MEM_SIZE; i++) mem[i] = 0x21; // 33 in decimals } }; #endif Error printout # Model Technology ModelSim PE sccom 10.4a compiler 2015.03 Mar 25 2015 # # In file included from source/testbench/../module/c/memory.h:11, # from source/testbench/cpu_testbench.h:11, # from source/testbench/cpu_testbench.cpp:5: # source/testbench/../module/c/rtl_to_tlm2_adaptor.h: In member function 'void rtl_to_tlm2_adaptor::local_b_transport()': # source/testbench/../module/c/rtl_to_tlm2_adaptor.h:148: error: no matching function for call to 'tlm::tlm_fw_transport_if<tlm::tlm_base_protocol_types>::b_transport(tlm::tlm_generic_payload&, sc_core::sc_time)' # C:/modeltech_pe_10.4a\include\systemc/tlm_core/tlm_2/tlm_2_interfaces/tlm_fw_bw_ifs.h:54: note: candidates are: void tlm::tlm_blocking_transport_if<TRANS>::b_transport(TRANS&, sc_core::sc_time&) [with TRANS = tlm::tlm_generic_payload]
  5. Hello, I used b_transport in of my TL models to exchange data from a transactor to a memory. It was a read/write/reset operation kinda thing. Data from memory is transferred to another module attached to the transactor. What I noticed was at the end of my b_transport call, the simulation ends directly, without returning to the transactor thread in order to affect the obtained data from memory (in case of a read operation, for example) to the port connecting the transactor and the other module. Why is this? Code for reference: memory // TLM-2 blocking transport method virtual void b_transport(tlm::tlm_generic_payload& trans, sc_time& delay) { /** Code here to transfer data **/ // Realize wait delay to advance simulation time wait(delay); // After wait, the simulator goes directly back to sc_main } transactor void thread_process() { /** Code here **/ while(true) { wait(CLK->posedge_event()); // Wait on CLK posedge event /** More code here **/ payload_setup(trans, cmd, data_ref, addr); rtt2a_socket->b_transport(*trans, delay); // Blocking transport call. Trans is a generic payload // I expected the program to return here, but it didn't // Initiator obliged to check response status and delay if (trans->is_response_error()) SC_REPORT_ERROR("TLM-2", "Response error from b_transport"); if(cmd == tlm::TLM_READ_COMMAND) DATA->write(d_word_t(data)); // Write data back to port. So far, this does not work properly } Thank you,
  6. Hi All, I'm quite new to TLM and have just joined this forum. I'd appreciate if you could help me to clarify one probably very simple question. I have N targets and one initiator. Each target handles transactions of particular priority. I need to analyze several transactions, arriving at these targets in one delta-cycle, select one with the highest priority and send it from the only one initiator. Priorities can change dynamically. Can you please share your ideas on that? Thank you in advance, Evgeniy
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