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Found 6 results

  1. Hi, I have declared and defined the clock in my example and able to generate and transport the transactions successfullly. As its is a blocking transport interface of tlm,so we are using wait statement. But what i observed here is, i am not able to control the triggering of process by using clocks for both the modules.Thiugh , i am able to controll the thread awakening by using delay statements. What if i want to use clocks to controll the trigger ,thats why i had put them in the sensitivity list. Please let me know,what would be my approach for the triggering b
  2. Hello Guys I have a scenario where I have an initiator module on SystemC side and target module on UVL side. From initiator side, I call b_transport with some payload and in target side the data field is modified. What I am seeing that when b_transport returns on initiator module, the changes in data field is not reflected. On SystemC side, I have a thread with following function void run(){ int i = 4; while(i--){ cout<<" in run........"<<endl; tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload; sc_time delay = sc_time(100,
  3. Hello, I've scoured the internet and this forum for what I imagine will have a very simple solution. Apparently I am not describing it sufficiently. I have a SystemC model comprised of a handful of registers, and single memory bank. I would like to implement TWO blocking transport interfaces to this model. If I implement a single blocking transport ( via inheritance of b_transport ), the method has access to all the model resources. If I want two b_transport interfaces, I've had to move them to channels, which are then instantiated in the model. These channels do not have ac
  4. Hello, I'm trying to compile a design with a TLM2 socket (simple_initiator_socket) in ModelSim (sccom). So far, the compiler returns an error saying that there is no function called b_transport. Yet I have this same design working in the PoC SC simulator, so I'm guessing that ModelSim is doing things differently than the PoC. However ModelSim does point out an alternative, which was to use blocking_transport_if's version. I believe this was the one used all along in the PoC, and it should be the same in ModelSim. Any ideas? Here are the designs: Initiator /** * RTL-t
  5. Hello, I used b_transport in of my TL models to exchange data from a transactor to a memory. It was a read/write/reset operation kinda thing. Data from memory is transferred to another module attached to the transactor. What I noticed was at the end of my b_transport call, the simulation ends directly, without returning to the transactor thread in order to affect the obtained data from memory (in case of a read operation, for example) to the port connecting the transactor and the other module. Why is this? Code for reference: memory // TLM-2 blocking transport method virt
  6. Hi All, I'm quite new to TLM and have just joined this forum. I'd appreciate if you could help me to clarify one probably very simple question. I have N targets and one initiator. Each target handles transactions of particular priority. I need to analyze several transactions, arriving at these targets in one delta-cycle, select one with the highest priority and send it from the only one initiator. Priorities can change dynamically. Can you please share your ideas on that? Thank you in advance, Evgeniy
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