joniale
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From http://www.asic-world.com/systemverilog/literal_values4.html string a; a = "This is multi line comment \n and this is second line"; /* Outputs: a = This is multi line comment^M and this is second line */ //You will have ^M which is the dos character for new line. if you write to a file with this line. If you want to avoid that, then the next solution should be used string tmg ={" \n" , "//periodic signal intf.KEYCONTROL_CLK \n" , "fork\n"
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Any DPI which can call Python in verilog testbench?
joniale replied to wilson_on's topic in UVM SystemVerilog Discussions
A good tutorial to understand how to embedd Python in C https://www6.software.ibm.com/developerworks/education/l-pythonscript/l-pythonscript-ltr.pdf Then you can search how to use DPI with C to be able to use C in systemverilog. Sure, There is a lot of DPI examples in your vendor EDA simulator folder. -
Maybe an error on UVM 1.1d for uvm_reg_map.svh class
joniale replied to joniale's topic in UVM SystemVerilog Discussions
Hi again, I want to report another minor issue. the issue is applicable in case you want a layering sequence for registers in AXI. I mean what is described here: https://www.mentor.com/products/fv/resources/overview/a-new-class-of-registers-2e32ca83-d5ee-4e34-8880-c006be7e537f As you can see a layering sequence allows you to create randomized register accesses that are not possible with the adapter and the default uvm_reg_map. This is needed to test that registers are written/read correctly with different AXI accessed than the fix accesses done by the uvm library. -
joniale reacted to a post in a topic:
What is the proper way to trigger something when a uvm_reg field is written?
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Starting sequences on null sequencer?
joniale replied to cliffc's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi experts, I have the following question about vertical reusability and null sequencers. I have a sequence that stimulates a sub block inside a TOP block. I have verified first the separated sub block. Therefore, i had a testbench for the sub block that has of course VC interfaces and registers. I would like to have a clear way of coding to allow vertical reusability of the sequence that test the sub block. In other words, i would like how to code the sub sequence so that i can start that sequence from a TOP module afterwards. I see the following problems 1)The TOP te -
Here my two cents, In my opinion, it would be good that UVM would do the backdoor access not as it currently does. It would be good that once provided the hdl_path to a field, the UVM library somehow would be able to generate an unique interface for that hdl_path and a bind that correspond to that interface. That generated interface should be published to the config data base and would be available in any part of your design through the ConfigDB. Of course, the UVM backdoor functions would still be able to do the checks they do now, for example, check that the register is not being acces
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cloning a register
joniale replied to assafgedalia's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi, Here my two cents. Cloning of register blocks is not intended in UVM. Therefore, there are several checkers that warns you about that. One way to do this is implementing a custom clone function inside the register block for each field. This is something that can be done with some perl scripting (if you have many registers and fields). See a small snip on how to do that (only with one register and field EXPECTED_SUM_2) class hmac_sha256_regblock extends uvm_reg_block; `uvm_object_utils(hmac_sha256_regblock) //This function has been included in the au -
joniale reacted to a post in a topic:
UVM reg model mask
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Hi , To whom may correspond I think there is some kind of error in the UVM 1.1d register model. I have been experimenting with the UVM register model and i have seen the following code in uvm_reg_map.svh task uvm_reg_map::do_bus_write (uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter); uvm_reg_addr_t addrs[$]; uvm_reg_map system_map = get_root_map(); int unsigned bus_width = get_n_bytes(); uvm_reg_byte_en_t byte_en = -1; uvm_reg_map_info map_info;
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UVM register model: Field access and bus2reg
joniale replied to joniale's topic in UVM (Pre-IEEE) Methodology and BCL Forum
You can avoid the display of the warning coming from the regmodel using the UVM component function uvm_top.set_report_severity_id_action(UVM_WARNING, "RegModel", UVM_NO_ACTION); However, this will disable all warnings coming from RegModel ID. Best regards, Jonathan -
UVM register model: Field access and bus2reg
joniale replied to joniale's topic in UVM (Pre-IEEE) Methodology and BCL Forum
In case you are using a direct VC burst I guess the way to do this is by expanding/padding the original partial access to a register and make it access the whole register. The padding can make use of byte_en to flag those extra bytes as dummy. This can be done, either in the monitor or by overwritting the uvm_reg_predictor class (creating a split/padding adapter function). In case you use the UVM register write function to write a field of a register: With the configuration 1byte per address and a register of 4 bytes. First field in the first byte. The reason why the moni -
Dear Accellera developers, I have been working with the register model since some weeks. I have tried to understand how the adapters were supposed to be used for all the possible combinations of accesses and register definitions. After those weeks I still have some questions. Lets assume we have a register of 32bits with 3 fields. The databytes per address granularity is 1 databyte per increment of address. In other words, each address increment corresponds to one data byte written . That means that a 32bit register comprises 4 address per register. We have a protoc
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Guideline of using uvm objection
joniale replied to ranjisan's topic in UVM (Pre-IEEE) Methodology and BCL Forum
There are some problems on adding objections in the Master driver and monitor. (slave should not have objections as they are reactive) See https://verificationacademy.com/forums/uvm/question-regarding-dropping-objections-once-stopsequences-issued-sequencer This problem is seen once you start doing asynchronous reset. If you do that then you have to drop the objections in a controlled way (if you currently has an ongoing xfer/raised objection on the driver). This would be difficult if you are using the disable fork or stop_sequences method for controlling the reset. These two methods, sto -
ljepson74 reacted to a post in a topic:
randomize a string ?
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Here a small example of code: First, an example to create a byte dynamic array from a string. The dynamic array of bytes contains the ASCII CODE number representation of each character. The advantage is that this can be for example be randomized but strings cannot be randomized. (created doing e.g. for(i=0;i<stringvar.len(); i++) begin byte_din_array = {byte_din_array ,stringvar[i]}; //stringvar[i] will return empty byte if the index would be beyond the string length //The advantage of using stringvar[i] instead of stringvar.atoi(i) is that //the string can have al
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Just to put it clearly you cannot change the parameters dynamically. That would not work. That is to say Your address in: class b_seq #(parameter bit [16:0] address = 0) extends base_seq need to be a constant or static not changing in the run_phase. In other words, a virtual sequencer or the task that will start this sequence cannot use a variable for this. If you want to pass info between seq classes you can just create rand class variables and set them with randomize with before you execute the sequence. you can also use `uvm_do_on_with(xfer_or_seq,sequencer {address==32'hABCD}); The
