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Showing results for tags 'iff'.
I recently encountered SVA code which results in different results on different simulators. I've shrunk it to a simple example here. I believe this code should cause an error, but it does not on all tools. Can someone comment on how the 2017 LRM should be interpreted (and perhaps on the code). (I sense someone will comment on the driving signals in the code.) module top; bit clk; logic sig1; logic disable_assert; always begin #5 clk=0; #5 clk=1; end initial begin disable_assert=1'b1; sig1 =1'b0; $display("Hello Wor
I happened across the following code. @(m_vif.smp_cb iff (m_vif.smp_cb.xyz_enable) ); To get to the crux of my question, let's consider it to be the below code. I don't think I've dropped anything relevant with this change (but I post both, b/c I have dropped important info with my edits in the past). @(posedge clk iff (xyz_enable) ); Q) How should the above line behave? How would you read that line aloud? 1) "Wait for a posedge of clk, if and only if xyz_enable is true." //That's how I read it, but that is incorrect. 2) "Wait for posedges of clk until xyz_enable is true."