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  1. https://verificationacademy.com/forums/uvm/how-turnoff-constraint-present-another-file-.
  2. Here is a sample code of what I'm working on class c_cfg extends uvm_object; rand bit c_bit; constraint c_turnoff { c_bit == 1'b0; } ........... endclass: c_cfg 2nd file class b_cfg extends uvm_object; rand c_cfg cfg_c; ........ ........ endclass: b_cfg main file class a_cfg extends b_cfg; // I want to overwrite the constraint in c_cfg here. // I want that to be 1 endclass: a_cfg I tried overwriting the constraint in c_cfg by using the same constraint name in a_cfg, but it doesn't solve (I guess it is because in c_cfg and not in b_cfg) simulator is not able to solve the constraint. Then tried cfg_c.c_turnoff.constraint_mode(0); in the new function in a_cfg, but it still considers the constraint in c_cfg. Can someone suggest how to do that. Thanks
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