UVM (Pre-IEEE) Methodology and BCL Forum

944 topics in this forum

1. Random stability issue with `uvm_info and changing verbosity

   By bughound, November 9, 2015   

   • Random stability
   • verbosity
   • (and 1 more)

     Tagged with:

     • Random stability
     • verbosity
     • uvm_info
   • 3 replies
   • 2.4k views
   • 
   • bughound
   • November 13, 2015

2. uvm_config_db and hierarchical access

   By ljepson74, October 24, 2015   

   • uvm_config_db
   • hierarchical access
   • (and 5 more)

     Tagged with:

     • uvm_config_db
     • hierarchical access
     • dot notation
     • ::set
     • ::get
     • set
     • get
   • 3 replies
   • 3.3k views
   • 
   • c4brian
   • November 12, 2015

3. How to change verbosity of message during simulation?

   By mmistry, November 6, 2015
   • 2 replies
   • 9.3k views
   • 
   • mmistry
   • November 9, 2015

4. uvm register implimentation for same register with different instances

   By leomoon85, September 30, 2015   

   • uvm_reg
   • multiple register instances
   • 10 replies
   • 7.1k views
   • 
   • karandeep963
   • November 7, 2015

5. Test / Sim Farm

   By c4brian, November 5, 2015
   • 2 replies
   • 1.1k views
   • 
   • tudor.timi
   • November 6, 2015

6. Transaction Recording in Cadence

   By leelar, November 2, 2015
   • 0 replies
   • 1k views
   • 
   • leelar
   • November 2, 2015

7. referring/connecting env in a test

   By sathyakiran.p, October 24, 2015   

   • uvm_test
   • uvm_env
   • (and 1 more)

     Tagged with:

     • uvm_test
     • uvm_env
     • connect_phase
   • 1 reply
   • 1.1k views
   • 
   • sathyakiran.p
   • October 31, 2015

8. uvm_component apply_config_settings method limitation

   By sylvainb, October 19, 2015   

   • uvm_config_db
   • int
   • (and 1 more)

     Tagged with:

     • uvm_config_db
     • int
     • enum
   • 2 replies
   • 2.1k views
   • 
   • sylvainb
   • October 20, 2015

9. How do I raise objection to main phase in a component's run_phase()

   By walkeranderson, October 11, 2015
   • 1 reply
   • 2k views
   • 
   • tudor.timi
   • October 15, 2015

10. How to file a bug?

    By syosil_jacob, September 24, 2015   

    • Bug
    • TLM
    • (and 1 more)

      Tagged with:

      • Bug
      • TLM
      • Generic Payload
    • 3 replies
    • 1.4k views
    • 
    • tudor.timi
    • September 30, 2015

11. uvm sequence for slave implementation

    By Madhu, September 21, 2015   

    • uvm
    • slave
    • 2 replies
    • 3.6k views
    • 
    • ruchir.bharti
    • September 28, 2015

12. using uvm_config_db::get inside a module

    By assafgedalia, September 20, 2015
    • 1 reply
    • 2.7k views
    • 
    • uwes
    • September 21, 2015

13. uvm_mem_mam request/reserve region size

    By walkeranderson, September 12, 2015
    • 3 replies
    • 1.7k views
    • 
    • dave_59
    • September 14, 2015

14. uvm_builtin_reg_test_seq & default sequences

    By ljepson74, September 11, 2015   

    • uvm_builtin_reg_test_seq
    • register layer
    • (and 2 more)

      Tagged with:

      • uvm_builtin_reg_test_seq
      • register layer
      • uvm_reg
      • default sequence
    • 2 replies
    • 3.2k views
    • 
    • uwes
    • September 14, 2015

15. Different flow for uvm_recorder usage in uvm_component between UVM1.1 and UVM1.2

    By lianhuo, September 14, 2015   

    • recorder
    • 0 replies
    • 1.5k views
    • 
    • lianhuo
    • September 14, 2015

16. proper layering in an ethernet transaction class

    By c4brian, December 31, 2014   

    • ethernet polymorphism
    • 18 replies
    • 8.8k views
    • 
    • c4brian
    • September 11, 2015

17. UVM Sequence Help

    By marcodemi, September 8, 2015
    • 11 replies
    • 4.4k views
    • 
    • tudor.timi
    • September 10, 2015

18. extracting data from uvm_do_with macro

    By assafgedalia, September 8, 2015
    • 4 replies
    • 1.8k views
    • 
    • assafgedalia
    • September 8, 2015

19. UVM Monitor help!!!

    By Hongnhattl, July 16, 2015   

    • UVM Monitor
    • 21 replies
    • 7.5k views
    • 
    • Hongnhattl
    • September 4, 2015

20. controlled transition from one phase to another

    By anshulgarg, September 1, 2015   

    • uvm
    • phase
    • (and 1 more)

      Tagged with:

      • uvm
      • phase
      • transition of phase
    • 4 replies
    • 1.5k views
    • 
    • bhunter1972
    • September 2, 2015

21. How to set verbosity for uvm_object (not component)?

    By c4brian, September 1, 2015
    • 2 replies
    • 3.9k views
    • 
    • tudor.timi
    • September 1, 2015

22. Am I done testing yet? A (fun!) coverage question..

    By c4brian, August 21, 2015   

    • coverage
    • test plan
    • (and 1 more)

      Tagged with:

      • coverage
      • test plan
      • verification plan
    • 0 replies
    • 1k views
    • 
    • c4brian
    • August 21, 2015

23. Multiple +uvm_set_severity are ignored

    By ofird, August 18, 2015
    • 2 replies
    • 2.3k views
    • 
    • ofird
    • August 19, 2015

24. What 's difference between copy and clone?

    By hugemx830202, May 15, 2011
    • 3 replies
    • 22k views
    • 
    • nicolbiden
    • August 8, 2015

25. phase jump to function phases

    By anming, July 23, 2015
    • 4 replies
    • 3.8k views
    • 
    • ruchir.bharti
    • August 3, 2015