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marcodemi

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  1. Hi Tudor, I have a similar problem but I do not understand the solution you proposed. If I need to read a certain internal signal, supposing this signal is "sig" inside a DUT submodule "sub 1". Where should I put that specific signal? In which way? Thank you in advance
  2. I use the function new inside the Sequencer class. Then I have instantiated Sequencer in the Environment class and there I use the create method. In my t_env class Seqncr is instantiated as follows: class Environment extends uvm_env; `uvm_component_utils(Environment) Sequencer Seqncr; Driver Drvr; function new(string name, uvm_component parent = null); super.new(name,parent); endfunction: new virtual function void build(); super.build(); uvm_report_info(get_full_name(),"START of build ",UVM_LOW); Drvr = Driver::type_id::create("Drvr",this); Seqncr = Sequencer::type_id::create("Seqncr",this); endfunction : build Packet is declared as class. class Packet extends uvm_sequence_item
  3. Thank you, it worked. The new UVM fatal is the following: "UVM_FATAL ./sequence_macsec_tx.sv(11) @ 0: uvm_test_top.t_env.Seqncr@@Sequence0 [DCLPSQ] \$unit ::\Sequence0::m_set_p_sequencer uvm_test_top.t_env.Seqncr.Sequence0 Error casting p_sequencer, please verify that this sequence/sequenceitem is intended to execute on this type of sequencer (type pseq class $unit::Sequencer: type mseq class uvm_pkg::uvm_sequencer_base)"
  4. With full example you mean other parts of the environment? I tried to upgrade the DCLPSQ as suggested `define uvm_declare_p_sequencer(SEQUENCER) \ SEQUENCER p_sequencer;\ virtual function void m_set_p_sequencer();\ super.m_set_p_sequencer(); \ if( !$cast(p_sequencer, m_sequencer)) \ `uvm_fatal("DCLPSQ", \ $sformatf({"%m %s Error casting p_sequencer, please verify that this sequence/sequence"\ "item is intended to execute on this type of sequencer(type pseq %s: type mseq %s)"}, get_full_name(),`uvm_typename(p_sequencer),`uvm_typename(m_sequencer))) \ endfunction but I am getting the following error "Error-[sE] Syntax error Following verilog source has syntax error : Instances are not allowed in compilation-unit scope/$unit "../../uvm-1.2//src/macros/uvm_sequence_defines.svh", 455: token is ')' get_full_name(),`uvm_typename(p_sequencer),`uvm_typename(m_sequencer))) \ ^ VCS addresses an ambiguity in module instances located outside of modules. All module instances must be inside a module. For more information, please see the SolvNet article on module instances and compilation units."
  5. Thanks for your reply. I tried to do as suggested but I am getting the same error. Below there is my Sequencer class Sequencer extends uvm_sequencer #(Packet); Configuration cfg; `uvm_sequencer_utils(Sequencer) function new (string name, uvm_component parent); super.new(name,parent); `uvm_update_sequence_lib_and_item(Packet) endfunction : new virtual function void end_of_elaboration(); uvm_object tmp; assert(get_config_object("Configuration",tmp)); $cast(cfg,tmp); endfunction endclass : Sequencer
  6. Hi all, I am experiencing a problem with sequence/sequencer. I think that the problem is inside the sequence class Sequence0 extends uvm_sequence #(Packet); function new(string name = "Sequence0"); super.new(name); `uvm_info(get_full_name(), "Sequence new()",UVM_LOW); endfunction : new Packet item; `uvm_sequence_utils(Sequence0, Sequencer) virtual task body(); forever begin `uvm_info(get_full_name(), "Sequence build()",UVM_LOW); `uvm_do_with(item,{da.size == 6;}); end endtask : body endclass : Sequence0 The compilation works; on the other side the run phase shows a "UVM_FATAL ./sequence_macsec_tx.sv(11) @ 0: uvm_test_top.t_env.Seqncr@@Sequence0 [DCLPSQ] \$unit ::\Sequence0::m_set_p_sequencer uvm_test_top.t_env.Seqncr.Sequence0 Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer" I inserted on purpose the `uvm_info and the last message that I get is Sequence new() as stated in line 5. Do you have any idea about the above error? Thanks in advance
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