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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

934 topics in this forum

  1. How to report bugs and enhancement requests for UVM

    By Tom_Alsop,
    • 3 replies
    • 4,829 views

  2. uvm_comparer::compare_field_int() False Pass with size

    By aelms,
    • 1 reply
    • 452 views

  3. UVM Reg Model: access register error using bitbash seq because of predictor

    By Chris Le,
    • 3 replies
    • 1,087 views

  4. Not able to configure thru +uvm_set_config_int:

    By kamboj,
    • 9 replies
    • 8,044 views

  5. get_starting_phase() vs starting seq with uvm_config_db

    By DV-E,
    • 0 replies
    • 232 views

  6. Address Map as submap to multiple address maps

    By Anil Kumar,   
    • 2 replies
    • 403 views

  7. set_type_override and set_inst_override usage inconsistency

    By chintanm86,
    • 2 replies
    • 610 views

  8. User defines frontdoor sequence can't support simultaneous accesses

    By ddayan14,
    • 10 replies
    • 1,681 views

  9. UVM factory usage recommendation inconsistent with base class implementation.

    By aelms,
    • 0 replies
    • 369 views

  10. Starting sequences on null sequencer?

    By cliffc,   
    • 8 replies
    • 7,589 views

  11. What is the proper way to trigger something when a uvm_reg field is written?

    By dwikle,
    • 7 replies
    • 15,910 views

  12. How to send sequence instead of stream of sequence_item?

    By soloist_huaxin,
    • 0 replies
    • 348 views

  13. cloning a register

    By assafgedalia,
    • 4 replies
    • 1,695 views

  14. uvm_object::set_int_local for static integer array

    By Robert.g.Liu,
    • 1 reply
    • 619 views

  15. Enabling inbuilt UVM RAL coverage sampling

    By gaurav_brcm,
    • 3 replies
    • 3,137 views

  16. Two sequences getting sequencer.lock grant in the same simulation cycle

    By b0rna,   
    • 0 replies
    • 816 views

  17. UVM print with array objects

    By mwhite_cp,
    • 7 replies
    • 7,145 views

  18. UVM register model: Field access and bus2reg

    By joniale,   
    • 2 replies
    • 2,181 views

  19. UVM register access with multiple masters to same register model

    By qwerty,
    • 3 replies
    • 1,049 views

  20. How to set a virtual interface of a VIP from SoC tb top

    By rudra2255,   
    • 0 replies
    • 821 views

  21. uvm_mem depth configuration

    By qwerty,
    • 1 reply
    • 660 views

  22. What would be the strategy to verify

    By karandeep963,
    • 1 reply
    • 805 views

  23. issues about Construction a verification environment for specific modules

    By thanhvanchi,
    • 1 reply
    • 846 views

  24. Instance override RAL adapter transaction objects?

    By kaushalmodi,   
    • 7 replies
    • 1,261 views

  25. Problem about Setting UVM severity

    By thanhvanchi,
    • 1 reply
    • 1,037 views
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