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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

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937 topics in this forum

  1. UVM IEEE v1.1 kill() and m_kill()

    By DV-E,
    • 0 replies
    • 14 views

  2. Pipelined RAL access

    By Kamlesh Shah,
    • 5 replies
    • 3.4k views

  3. UVM Register Field Coverage

    By graeme_jessiman,
    • 8 replies
    • 8.7k views

  4. X's in mirrored value (UVM hardware reset sequence)

    By gaurav_brcm,   
    • 8 replies
    • 2.8k views

  5. UVM's m_sequencer, p_sequencer, get_sequencer() and `uvm_declare_p_sequencer

    By cliffc,
    • 8 replies
    • 32.2k views

  6. how to report tool(vcs/ncsim..)/assertion related errors in UVM

    By sathyakiran.p,   
    • 4 replies
    • 3.7k views

  7. sequencer grab/ungrab not behaving according to specs

    By StefanoEsposito,
    • 1 reply
    • 166 views

  8. multiple threads calling sequencer lock results in deadlock

    By Lawrence Said,   
    • 0 replies
    • 196 views

  9. How to report bugs and enhancement requests for UVM

    By Tom_Alsop,
    • 3 replies
    • 5k views

  10. uvm_comparer::compare_field_int() False Pass with size

    By aelms,
    • 1 reply
    • 650 views

  11. UVM Reg Model: access register error using bitbash seq because of predictor

    By cuonghl,
    • 3 replies
    • 1.7k views

  12. Not able to configure thru +uvm_set_config_int:

    By kamboj,
    • 9 replies
    • 9k views

  13. get_starting_phase() vs starting seq with uvm_config_db

    By DV-E,
    • 0 replies
    • 448 views

  14. Address Map as submap to multiple address maps

    By Anil Kumar,   
    • 2 replies
    • 899 views

  15. set_type_override and set_inst_override usage inconsistency

    By chintanm86,
    • 2 replies
    • 1.3k views

  16. User defines frontdoor sequence can't support simultaneous accesses

    By ddayan14,
    • 10 replies
    • 2.1k views

  17. UVM factory usage recommendation inconsistent with base class implementation.

    By aelms,
    • 0 replies
    • 562 views

  18. Starting sequences on null sequencer?

    By cliffc,   
    • 8 replies
    • 9.4k views

  19. What is the proper way to trigger something when a uvm_reg field is written?

    By dwikle,
    • 7 replies
    • 17.9k views

  20. How to send sequence instead of stream of sequence_item?

    By soloist_huaxin,
    • 0 replies
    • 460 views

  21. cloning a register

    By assafgedalia,
    • 4 replies
    • 2.1k views

  22. uvm_object::set_int_local for static integer array

    By Robert.g.Liu,
    • 1 reply
    • 968 views

  23. Enabling inbuilt UVM RAL coverage sampling

    By gaurav_brcm,
    • 3 replies
    • 4.1k views

  24. Two sequences getting sequencer.lock grant in the same simulation cycle

    By b0rna,   
    • 0 replies
    • 1.2k views

  25. UVM print with array objects

    By mwhite_cp,
    • 7 replies
    • 7.9k views
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