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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

936 topics in this forum

  1. X's in mirrored value (UVM hardware reset sequence)

    By gaurav_brcm,   
    • 8 replies
    • 2,514 views

  2. UVM's m_sequencer, p_sequencer, get_sequencer() and `uvm_declare_p_sequencer

    By cliffc,
    • 8 replies
    • 31,098 views

  3. how to report tool(vcs/ncsim..)/assertion related errors in UVM

    By sathyakiran.p,   
    • 4 replies
    • 3,478 views

  4. sequencer grab/ungrab not behaving according to specs

    By StefanoEsposito,
    • 1 reply
    • 116 views

  5. multiple threads calling sequencer lock results in deadlock

    By Lawrence Said,   
    • 0 replies
    • 89 views

  6. How to report bugs and enhancement requests for UVM

    By Tom_Alsop,
    • 3 replies
    • 4,964 views

  7. uvm_comparer::compare_field_int() False Pass with size

    By aelms,
    • 1 reply
    • 573 views

  8. UVM Reg Model: access register error using bitbash seq because of predictor

    By cuonghl,
    • 3 replies
    • 1,387 views

  9. Not able to configure thru +uvm_set_config_int:

    By kamboj,
    • 9 replies
    • 8,565 views

  10. get_starting_phase() vs starting seq with uvm_config_db

    By DV-E,
    • 0 replies
    • 338 views

  11. Address Map as submap to multiple address maps

    By Anil Kumar,   
    • 2 replies
    • 638 views

  12. set_type_override and set_inst_override usage inconsistency

    By chintanm86,
    • 2 replies
    • 921 views

  13. User defines frontdoor sequence can't support simultaneous accesses

    By ddayan14,
    • 10 replies
    • 1,903 views

  14. UVM factory usage recommendation inconsistent with base class implementation.

    By aelms,
    • 0 replies
    • 482 views

  15. Starting sequences on null sequencer?

    By cliffc,   
    • 8 replies
    • 8,696 views

  16. What is the proper way to trigger something when a uvm_reg field is written?

    By dwikle,
    • 7 replies
    • 17,058 views

  17. How to send sequence instead of stream of sequence_item?

    By soloist_huaxin,
    • 0 replies
    • 412 views

  18. cloning a register

    By assafgedalia,
    • 4 replies
    • 1,872 views

  19. uvm_object::set_int_local for static integer array

    By Robert.g.Liu,
    • 1 reply
    • 818 views

  20. Enabling inbuilt UVM RAL coverage sampling

    By gaurav_brcm,
    • 3 replies
    • 3,748 views

  21. Two sequences getting sequencer.lock grant in the same simulation cycle

    By b0rna,   
    • 0 replies
    • 1,039 views

  22. UVM print with array objects

    By mwhite_cp,
    • 7 replies
    • 7,611 views

  23. UVM register model: Field access and bus2reg

    By joniale,   
    • 2 replies
    • 2,706 views

  24. UVM register access with multiple masters to same register model

    By qwerty,
    • 3 replies
    • 1,274 views

  25. How to set a virtual interface of a VIP from SoC tb top

    By rudra2255,   
    • 0 replies
    • 923 views
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