walkeranderson
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Pipelined RAL access
walkeranderson replied to Kamlesh Shah's topic in UVM (Pre-IEEE) Methodology and BCL Forum
FWIW, Later yesterday I found this bug logged which seems to be the same thing. http://www.eda.org/svdb/view.php?id=4820 -
Pipelined RAL access
walkeranderson replied to Kamlesh Shah's topic in UVM (Pre-IEEE) Methodology and BCL Forum
I just hit this same problem and tracked it down to the same underlying problem in the UVM code. This change, to both the do_bus_read() and do_bus_write() tasks in uvm_reg_map.svh, seemed to fix it for me. Changed: rw.parent.get_base_response(bus_rsp); to: rw.parent.get_base_response(bus_rsp, bus_req.get_transaction_id()); Any comments on whether this is a bug or not. It is not changed/fixed in the UVM 1.2 release.