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cschmitt

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  1. Does the UVM register model have support for shadow registers? In my DUT there are a few registers that have shadows, ie. on a write the shadow register is written and this value is not transferred to the actual register until another event (in this case a third register gets written). As a result, the built-in bit bash test is failing because it thinks the actual register is not being written correctly: write(AREG, 3); -> writes 3 to AREG_SHADOW read(AREG, data); -> reads from AREG which still has the original value
  2. The UVM testbench I am working on uses an I2C interface to program registers in the DUT. I currently have the register model working for basic reads and writes. However, one of the features in the design allows for burst access to registers. For example, I could send the CTL register address on the I2C bus and then send several bytes of data. The first byte would go to the CTL register, and the design would auto-increment the address so the next byte would go to the next register. Is there a way to implement this burst access with the register model?
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