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uvm_reg::write updates regmodel in explicit prediction mode

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When using UVM register layer with predictor and bus adapter, in explicit prediction mode(implicit prediction disabled by setting auto_predict to 0),  uvm_reg::write task directly updates register model value(mirror register), at the same moment when write task is called before transaction is completed on the bus interface.

In explicit prediction mode, uvm_reg::write should only launch transaction on bus agent, then predictor will wait for transaction to be collected by bus monitor and only then update regmodel.

This worked well in UVM-1.0. but it doesn't work from UVM-1.1.


Inside uvm_reg::write task, unconditional call of set(value) function has been added in UVM-1.1, and this function updates regmodel value regardless the auto_predict setting.

uvm_reg::write in UVM-1.0 had only call of do_write() at the end, which takes into account auto_predict mode setting.



Has someone else noticed this issue? Is this known bug in UVM register layer?






task uvm_reg::write(output uvm_status_e      status,
                    input  uvm_reg_data_t    value,
                    input  uvm_path_e        path = UVM_DEFAULT_PATH,
                    input  uvm_reg_map       map = null,
                    input  uvm_sequence_base parent = null,
                    input  int               prior = -1,
                    input  uvm_object        extension = null,
                    input  string            fname = "",
                    input  int               lineno = 0);

   // create an abstract transaction for this operation
   uvm_reg_item rw;



   rw = uvm_reg_item::type_id::create("write_item",,get_full_name());
   rw.element      = this;
   rw.element_kind = UVM_REG;
   rw.kind         = UVM_WRITE;
   rw.value[0]     = value;
   rw.path         = path;
   rw.map          = map;
   rw.parent       = parent;
   rw.prior        = prior;
   rw.extension    = extension;
   rw.fname        = fname;
   rw.lineno       = lineno;


   status = rw.status;





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If we want to turn off implicit prediction, write will still call this set function and update mirror registre value. IMO this is not the way it should work. In explicit prediction mode mirror register should be updated only after transaction is collected on the bus interface.

What is the meaning of having both set and do_predict(in do_write)?

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If you've worked with vr_ad or some other register package in the past, you have to keep in mind that UVM REG works differently. There aren't mirror registers and temporary registers you use for sequences. There are only the model registers. These registers have 2 values they keep track of: desired value and mirrored value. The desired value is what you want to drive into the RTL and the mirrored value is what you think is in the RTL. Calling 'set()' doesn't update the mirrored value (i.e. the model), just the desired value. The user guide has a section on this that you should read for more details.

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By the wording of the  uvm_users_guide_1.1.pdf, chapter 5.9 Integrating a Register Model, there are 3 ways for keeping regmodel(miror values) in sync with DUT registers: implicit prediction, explicit prediction, and passive.

Implicit : Updates to the mirror are predicted automatically (i.e., implicitly) by the register model after the completion of each read, write, peek, or poke operation.

Explicit: implicit prediction is turned off and all updates to the mirror are predicted externally (i.e., explicitly) by a uvm_reg_predictor component


Do you agree that when implicit prediction is turned off  reg:write should not update regmodel(mirror value)?

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uvm_reg::set() calls for each field  uvm_reg_field::set(), and this function beside m_desired updates also uvm_reg_field.value which should represent mirrored value of the field.


from UVM_1.1_Class reference, uvm_reg_field summary:

value Mirrored field value


function void uvm_reg_field::set


      "WO1":   m_desired = (m_written) ? m_desired : value;
      default: m_desired = value;
   this.value = m_desired;
endfunction: set

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  • 5 weeks later...

Hi Alex,


I agree with the your inference that only during implicit prediction the register values in RAL should automatically updated after a write/set call.

And in explicit prediction the transaction items from monitors should trigger the update of the register layer. That was the whole idea of explicit prediction.


In my setup  of  explicit prediction (UVM 1.1) and even after disabling the auto prediction, I am noticing that there is one extra BUS2REG call being made beside the one by the monitor. And

The worst thing is that the values updated in Reg Layer is not updated as per the Monitor’s call but by the one which is called the write/set call (may be).


Tudor/Alex can you suggest me something here.

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