Alex Posted October 16, 2015 Report Share Posted October 16, 2015 When using UVM register layer with predictor and bus adapter, in explicit prediction mode(implicit prediction disabled by setting auto_predict to 0), uvm_reg::write task directly updates register model value(mirror register), at the same moment when write task is called before transaction is completed on the bus interface. In explicit prediction mode, uvm_reg::write should only launch transaction on bus agent, then predictor will wait for transaction to be collected by bus monitor and only then update regmodel. This worked well in UVM-1.0. but it doesn't work from UVM-1.1. Inside uvm_reg::write task, unconditional call of set(value) function has been added in UVM-1.1, and this function updates regmodel value regardless the auto_predict setting. uvm_reg::write in UVM-1.0 had only call of do_write() at the end, which takes into account auto_predict mode setting. Has someone else noticed this issue? Is this known bug in UVM register layer? Regards, Alex task uvm_reg::write(output uvm_status_e status, input uvm_reg_data_t value, input uvm_path_e path = UVM_DEFAULT_PATH, input uvm_reg_map map = null, input uvm_sequence_base parent = null, input int prior = -1, input uvm_object extension = null, input string fname = "", input int lineno = 0); // create an abstract transaction for this operation uvm_reg_item rw; XatomicX(1); set(value); rw = uvm_reg_item::type_id::create("write_item",,get_full_name()); rw.element = this; rw.element_kind = UVM_REG; rw.kind = UVM_WRITE; rw.value = value; rw.path = path; rw.map = map; rw.parent = parent; rw.prior = prior; rw.extension = extension; rw.fname = fname; rw.lineno = lineno; do_write(rw); status = rw.status; XatomicX(0);endtask Quote Link to comment Share on other sites More sharing options...
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