UVM Sequence Help

[marcodemi]

Hi all,

 

I am experiencing a problem with sequence/sequencer. I think that the problem is inside the sequence

class Sequence0 extends uvm_sequence #(Packet);

  function new(string name = "Sequence0");
		super.new(name);
		`uvm_info(get_full_name(), "Sequence new()",UVM_LOW);
	endfunction : new

	Packet item;
   
	 	
  `uvm_sequence_utils(Sequence0, Sequencer) 
        
	
	virtual task body();
    forever begin
		    `uvm_info(get_full_name(), "Sequence build()",UVM_LOW);           
			`uvm_do_with(item,{da.size == 6;}); 
                     
  	end
	endtask : body
	
endclass : Sequence0

The compilation works; on the other side the run phase shows a

 

"UVM_FATAL ./sequence_macsec_tx.sv(11) @ 0: uvm_test_top.t_env.Seqncr@@Sequence0 [DCLPSQ] \$unit ::\Sequence0::m_set_p_sequencer  uvm_test_top.t_env.Seqncr.Sequence0 Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer"

 

I inserted on purpose the `uvm_info and the last message that I get is Sequence new() as stated in line 5. 

 

Do you have any idea about the above error? 

 

Thanks in advance 

 

 

[tudor.timi]

As far as I remember, using `uvm_sequence_utils(...) isn't fashionable anymore. To avoid using deprecated features, change it to `uvm_object_utils(Sequence0) and `uvm_declare_p_sequencer(Sequencer).

 

Now, with respect to your problem, are you sure the sequencer you're starting the sequence on is of type Sequencer?

[marcodemi]

Thanks for your reply. I tried to do as suggested 

 

 

 change it to `uvm_object_utils(Sequence0) and `uvm_declare_p_sequencer(Sequencer).

 

but I am getting the same error. Below there is my Sequencer 

class Sequencer extends uvm_sequencer #(Packet);

	Configuration cfg;
	
	`uvm_sequencer_utils(Sequencer)
	
	function new (string name, uvm_component parent);
		super.new(name,parent);
		`uvm_update_sequence_lib_and_item(Packet)
	endfunction : new
	
	virtual function void end_of_elaboration();
		uvm_object tmp;
		assert(get_config_object("Configuration",tmp));
		$cast(cfg,tmp);
	endfunction
	
endclass : Sequencer

[uwes]

can you provide a full example? there are connectivity errors which finally result in such a message.

 

 

btw it also gets simpler if you use an upgraded variant of the DCLPSQ message which spits out the names of the types, etc

 

/uwe

 

diff --git a/distrib/src/macros/uvm_sequence_defines.svh b/distrib/src/macros/uvm_sequence_defines.svh

index b3f3f3e..24a0ad7 100644

--- a/distrib/src/macros/uvm_sequence_defines.svh

+++ b/distrib/src/macros/uvm_sequence_defines.svh

@@ -450,6 +450,8 @@

     super.m_set_p_sequencer(); \

     if( !$cast(p_sequencer, m_sequencer)) \

         `uvm_fatal("DCLPSQ", \

-        $sformatf("%m %s Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of

+        $sformatf({"%m %s Error casting p_sequencer, please verify that this sequence/sequence"\

+                               " item is intended to execute on this type of sequencer (type pseq %s: type mseq %s)"},

+get_full_name(),`uvm_typename(p_sequencer),`uvm_typename(m_sequencer))) \

   endfunction

[marcodemi]

With full example you mean other parts of the environment?

 

I tried to upgrade the DCLPSQ as suggested

`define uvm_declare_p_sequencer(SEQUENCER) \
  SEQUENCER p_sequencer;\
  virtual function void m_set_p_sequencer();\
    super.m_set_p_sequencer(); \
    if( !$cast(p_sequencer, m_sequencer)) \
        `uvm_fatal("DCLPSQ", \
        $sformatf({"%m %s Error casting p_sequencer, please verify that this sequence/sequence"\
				 "item is intended to execute on this type of sequencer(type pseq %s: type mseq %s)"}, 
				 get_full_name(),`uvm_typename(p_sequencer),`uvm_typename(m_sequencer))) \
  endfunction  

but I am getting the following error 

 

"Error-[sE] Syntax error

  Following verilog source has syntax error :

        Instances are not allowed in compilation-unit scope/$unit

  "../../uvm-1.2//src/macros/uvm_sequence_defines.svh", 455: token is ')'

                                 get_full_name(),`uvm_typename(p_sequencer),`uvm_typename(m_sequencer)))

\

                                                  ^

  VCS addresses an ambiguity in module instances located outside of modules.

  All module instances must be inside a module. For more information, please

  see the SolvNet article on module instances and compilation units." 

 

[uwes]

i think your code is missing a , (at the end of line 453)

[marcodemi]

Thank you, it worked. The new UVM fatal is the following:

 

"UVM_FATAL ./sequence_macsec_tx.sv(11) @ 0: uvm_test_top.t_env.Seqncr@@Sequence0 [DCLPSQ] 

\$unit ::\Sequence0::m_set_p_sequencer  uvm_test_top.t_env.Seqncr.Sequence0 Error casting p_sequencer, 

please verify that this sequence/sequenceitem is intended to execute on this type of sequencer

(type pseq class $unit::Sequencer: type mseq class uvm_pkg::uvm_sequencer_base)"

[apfitch]

How is Packet declared?

 

Alan

[tudor.timi]

Seems to me that you're starting it on a component of type uvm_sequencer_base instead of Sequencer. I'd check the type of your 'uvm_test_top.t_env.Seqncr' component.

[seabeam]

Did you ever new the sequencer?

[marcodemi]

Did you ever new the sequencer?

 

I use the function new inside the Sequencer class. Then I have instantiated Sequencer in the Environment class and there I use the create method. 

Seems to me that you're starting it on a component of type uvm_sequencer_base instead of Sequencer. I'd check the type of your 'uvm_test_top.t_env.Seqncr' component.

In my t_env class Seqncr is instantiated as follows:

class Environment extends uvm_env;

`uvm_component_utils(Environment)
		
		Sequencer Seqncr;
		Driver Drvr;
		
		function new(string name, uvm_component parent = null);
			super.new(name,parent);
		endfunction: new
		
		virtual function void build();
			super.build();
			
			uvm_report_info(get_full_name(),"START of build ",UVM_LOW);
			
			Drvr = Driver::type_id::create("Drvr",this);
			Seqncr = Sequencer::type_id::create("Seqncr",this);
                endfunction : build

How is Packet declared?

 

Alan

Packet is declared as class. 

class Packet extends uvm_sequence_item

[tudor.timi]

I guess the only thing left is to show us how you start your sequence.