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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

945 topics in this forum

  1. uvm_hdl_force error

    By qwerty,
    • 1 reply
    • 2.2k views

  2. uvm reg limitation

    By qwerty,
    • 3 replies
    • 1.4k views

  3. UVM Messages:: Controlling message using ID from top

    By tinku,
    • 1 reply
    • 2.1k views

  4. help needed how to do a backdoor access to individual fields in the register in UVM

    By rhegde,
    • 5 replies
    • 3.4k views

  5. how to start working with uvm

    By swathi92,
    • 5 replies
    • 1.2k views

  6. Problem about model in uvm_reg_sequence

    By mrforever,   
    • 2 replies
    • 2k views

  7. regarding objections

    By swathi92,
    • 1 reply
    • 1k views

  8. uvm_tlm_analysis_fifo issue

    By karandeep963,   
    • 7 replies
    • 3.1k views

  9. RAL Multiple Sequence

    By hvgbl,
    • 1 reply
    • 1.2k views

  10. uvm_config_db#(...) - Difference between set(null, "*", ...); -vs- set(uvm_root::get(), "*", ...); ??

    By cliffc,   
    • 1 reply
    • 11.4k views

  11. $sformatf

    By hvgbl,   
    • 3 replies
    • 13k views

  12. How to do multiple writes using uvm_hdl_force

    By qwerty,
    • 5 replies
    • 2.5k views

  13. How to override set_timeout

    By karandeep963,   
    • 3 replies
    • 2.9k views

  14. initialization sequence question

    By twk1156,
    • 9 replies
    • 2.5k views

  15. print() options

    By swathi92,
    • 1 reply
    • 1k views

  16. Using $display in UVM

    By cliffc,   
    • 6 replies
    • 3k views

  17. UVM reg model access policy of registers

    By qwerty,
    • 3 replies
    • 3.4k views

  18. UVM reg model mask

    By qwerty,
    • 10 replies
    • 9.8k views

  19. Channelized interface agent

    By ddayan,
    • 0 replies
    • 1k views

  20. Phase jump does not work as expected when multiple phases are running in parallel in different schedules.

    By mehtad,   
    • 1 reply
    • 1.6k views

  21. phase jumping happens for all active phases separately even if they belong to same domain.

    By mehtad,   
    • 3 replies
    • 2.6k views

  22. How to uvm_config_db to set parameter based interface down to my env?

    By hugemx830202,
    • 9 replies
    • 15.8k views

  23. override UVM phase?

    By jleng,
    • 2 replies
    • 3k views

  24. Generic Payload Vs PROTOCOL specific packets/seq_items in UVM env

    By karandeep963,
    • 1 reply
    • 1.7k views

  25. uvm_reg_map get_reg_by_offset() is misleading

    By tudor.timi,   
    • 0 replies
    • 8.3k views
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