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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

944 topics in this forum

  1. UVM register access with multiple masters to same register model

    By qwerty,
    • 3 replies
    • 2.2k views

  2. How to set a virtual interface of a VIP from SoC tb top

    By rudra2255,   
    • 0 replies
    • 1.2k views

  3. uvm_mem depth configuration

    By qwerty,
    • 1 reply
    • 1.2k views

  4. What would be the strategy to verify

    By karandeep963,
    • 1 reply
    • 1.2k views

  5. issues about Construction a verification environment for specific modules

    By thanhvanchi,
    • 1 reply
    • 1.2k views

  6. Instance override RAL adapter transaction objects?

    By kaushalmodi,   
    • 7 replies
    • 2.4k views

  7. Problem about Setting UVM severity

    By thanhvanchi,
    • 1 reply
    • 1.8k views

  8. UVM-REG Built-in Frontdoor and Bus byte enables computation issue?

    By jordan,   
    • 3 replies
    • 5.4k views

  9. uvm_reg_field W1C/W0S update problem

    By saxmanlogic,   
    • 2 replies
    • 5.4k views

  10. Are there any recommendations/guidelines on using UVM run sub phases?

    By mramdas,   
    • 0 replies
    • 1.2k views

  11. Complicated Register Modeling with uvm_reg

    By Logger,   
    • 0 replies
    • 2.3k views

  12. Why we get SEQREQZMB when jumping to another phase

    By zhiharev,
    • 2 replies
    • 4.2k views

  13. What is a proper way to set fields and update register in uvm register model?

    By timothy,   
    • 1 reply
    • 8k views

  14. Query related to UVM_RAL_REG model.

    By Kameshwar Rao,
    • 1 reply
    • 1.5k views

  15. issue about read write-only register via backdoor

    By mrforever,   
    • 1 reply
    • 4.3k views

  16. Usage of get_hdl_path() for backdoor register access

    By gaurav_brcm,
    • 0 replies
    • 3.2k views

  17. Communication between uvm_sequence and uvm_component

    By amar712,   
    • 3 replies
    • 2.8k views

  18. RAL mapping reg_field to another reg_field

    By defmaxou,
    • 1 reply
    • 992 views

  19. how to use uvm_in_order_comparator

    By mrforever,
    • 3 replies
    • 3.9k views

  20. priority for uvm_reg transactions

    By proo,   
    • 0 replies
    • 2k views

  21. multiple maps on ral class

    By elihai,   
    • 0 replies
    • 1.9k views

  22. Turn off `uvm_info messages

    By amar712,   
    • 3 replies
    • 3.6k views

  23. UVM Sequencer base class - Virtual task using local class variables - bad coding style?

    By sri.cvcblr,   
    • 1 reply
    • 1.7k views

  24. build_phase order

    By hevangel,   
    • 2 replies
    • 1.9k views

  25. Two grabbing sequences both win arbitration at the same time

    By walkeranderson,
    • 4 replies
    • 2.9k views
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