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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

944 topics in this forum

  1. cloning a register

    By assafgedalia,
    • 4 replies
    • 4.8k views

  2. uvm_object::set_int_local for static integer array

    By Robert.g.Liu,
    • 1 reply
    • 2k views

  3. Enabling inbuilt UVM RAL coverage sampling

    By gaurav_brcm,
    • 3 replies
    • 7.8k views

  4. Two sequences getting sequencer.lock grant in the same simulation cycle

    By b0rna,   
    • 0 replies
    • 2k views

  5. UVM print with array objects

    By mwhite_cp,
    • 7 replies
    • 12.2k views

  6. UVM register model: Field access and bus2reg

    By joniale,   
    • 2 replies
    • 7.7k views

  7. UVM register access with multiple masters to same register model

    By qwerty,
    • 3 replies
    • 2.6k views

  8. How to set a virtual interface of a VIP from SoC tb top

    By rudra2255,   
    • 0 replies
    • 1.4k views

  9. uvm_mem depth configuration

    By qwerty,
    • 1 reply
    • 1.5k views

  10. What would be the strategy to verify

    By karandeep963,
    • 1 reply
    • 1.4k views

  11. issues about Construction a verification environment for specific modules

    By thanhvanchi,
    • 1 reply
    • 1.4k views

  12. Instance override RAL adapter transaction objects?

    By kaushalmodi,   
    • 7 replies
    • 2.9k views

  13. Problem about Setting UVM severity

    By thanhvanchi,
    • 1 reply
    • 2.4k views

  14. UVM-REG Built-in Frontdoor and Bus byte enables computation issue?

    By jordan,   
    • 3 replies
    • 6.4k views

  15. uvm_reg_field W1C/W0S update problem

    By saxmanlogic,   
    • 2 replies
    • 6.6k views

  16. Are there any recommendations/guidelines on using UVM run sub phases?

    By mramdas,   
    • 0 replies
    • 1.5k views

  17. Complicated Register Modeling with uvm_reg

    By Logger,   
    • 0 replies
    • 3.1k views

  18. Why we get SEQREQZMB when jumping to another phase

    By zhiharev,
    • 2 replies
    • 5.8k views

  19. What is a proper way to set fields and update register in uvm register model?

    By timothy,   
    • 1 reply
    • 10.2k views

  20. Query related to UVM_RAL_REG model.

    By Kameshwar Rao,
    • 1 reply
    • 2k views

  21. issue about read write-only register via backdoor

    By mrforever,   
    • 1 reply
    • 4.9k views

  22. Usage of get_hdl_path() for backdoor register access

    By gaurav_brcm,
    • 0 replies
    • 4.2k views

  23. Communication between uvm_sequence and uvm_component

    By amar712,   
    • 3 replies
    • 3.4k views

  24. RAL mapping reg_field to another reg_field

    By defmaxou,
    • 1 reply
    • 1.2k views

  25. how to use uvm_in_order_comparator

    By mrforever,
    • 3 replies
    • 4.8k views
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