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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

935 topics in this forum

  1. uvm_random_stimulus usage

    By kumarv,
    • 4 replies
    • 1,282 views

  2. Disadvantages of abstract classes instead of virtual interfaces?

    By gbbrown,
    • 4 replies
    • 5,294 views

  3. Why doesn't this virtual interface connection crash and burn

    By mkorpi,   
    • 1 reply
    • 759 views

  4. multiple interfaces accessing the same uvm_reg

    By sudheerv,
    • 0 replies
    • 654 views

  5. Is this UVM register model bug being address? UVM/RSRC/NOREGEX

    By Logger,
    • 4 replies
    • 2,354 views

  6. reset_phase to be obsolete soon ?

    By chitlesh,   
    • 4 replies
    • 1,775 views

  7. Selection of specific physical interface in default UVM register layer sequences

    By nikunjhinsu,   
    • 2 replies
    • 1,509 views

  8. uvm_send is blocked even after driver executes item_done

    By ninad.pachpute,   
    • 8 replies
    • 4,219 views

  9. Guideline of using uvm objection

    By ranjisan,
    • 3 replies
    • 11,290 views

  10. Calling put_response when sequence that initiated sequence item has terminated

    By walkeranderson,
    • 1 reply
    • 789 views

  11. receiving null pointer error when accessing config object from uvm_do_with

    By assafgedalia,
    • 2 replies
    • 1,780 views

  12. Uvm filed macro

    By Nikhil,
    • 2 replies
    • 1,030 views

  13. Virtual Sequencer :: Sequencer Arbitration

    By tinku,
    • 0 replies
    • 672 views

  14. UVM Register Field Coverage

    By graeme_jessiman,
    • 7 replies
    • 7,538 views

  15. RAL. Mirroring registers with the same addresses

    By zhiharev,
    • 4 replies
    • 2,081 views

  16. OVM RGM Porting to UVM

    By ggupta,
    • 8 replies
    • 3,550 views

  17. (Possible) Bug in uvm_mem

    By tudor.timi,   
    • 3 replies
    • 1,812 views

  18. UVM Register Model Burst Access

    By cschmitt,
    • 5 replies
    • 7,203 views

  19. uvm_reg::write updates regmodel in explicit prediction mode

    By Alex,
    • 6 replies
    • 7,449 views

  20. Adding a run-time phase example

    By walkeranderson,
    • 1 reply
    • 771 views

  21. my test stuck in uvm sequence `uvm_send()

    By jakfens,   
    • 1 reply
    • 925 views

  22. Simulation speed/efficiency

    By c4brian,
    • 7 replies
    • 1,054 views

  23. Random stability issue with `uvm_info and changing verbosity

    By bughound,   
    • 3 replies
    • 1,556 views

  24. uvm_config_db and hierarchical access

    By ljepson74,   
    • 3 replies
    • 2,142 views

  25. uvm_vreg increment issues

    By mbecker,   
    • 1 reply
    • 2,218 views
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