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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

947 topics in this forum

  1. set_type_override and set_inst_override usage inconsistency

    By chintanm86,
    • 2 replies
    • 4.9k views

  2. User defines frontdoor sequence can't support simultaneous accesses

    By ddayan14,
    • 10 replies
    • 4.9k views

  3. UVM factory usage recommendation inconsistent with base class implementation.

    By aelms,
    • 0 replies
    • 1.2k views

  4. Starting sequences on null sequencer?

    By cliffc,   
    • 8 replies
    • 18.8k views

  5. What is the proper way to trigger something when a uvm_reg field is written?

    By dwikle,
    • 7 replies
    • 28.7k views

  6. How to send sequence instead of stream of sequence_item?

    By soloist_huaxin,
    • 0 replies
    • 1.1k views

  7. cloning a register

    By assafgedalia,
    • 4 replies
    • 5.5k views

  8. uvm_object::set_int_local for static integer array

    By Robert.g.Liu,
    • 1 reply
    • 2.3k views

  9. Enabling inbuilt UVM RAL coverage sampling

    By gaurav_brcm,
    • 3 replies
    • 9.2k views

  10. Two sequences getting sequencer.lock grant in the same simulation cycle

    By b0rna,   
    • 0 replies
    • 2.3k views

  11. UVM print with array objects

    By mwhite_cp,
    • 7 replies
    • 13.6k views

  12. UVM register model: Field access and bus2reg

    By joniale,   
    • 2 replies
    • 9k views

  13. UVM register access with multiple masters to same register model

    By qwerty,
    • 3 replies
    • 3.1k views

  14. How to set a virtual interface of a VIP from SoC tb top

    By rudra2255,   
    • 0 replies
    • 1.6k views

  15. uvm_mem depth configuration

    By qwerty,
    • 1 reply
    • 1.7k views

  16. What would be the strategy to verify

    By karandeep963,
    • 1 reply
    • 1.7k views

  17. issues about Construction a verification environment for specific modules

    By thanhvanchi,
    • 1 reply
    • 1.6k views

  18. Instance override RAL adapter transaction objects?

    By kaushalmodi,   
    • 7 replies
    • 3.5k views

  19. Problem about Setting UVM severity

    By thanhvanchi,
    • 1 reply
    • 2.9k views

  20. UVM-REG Built-in Frontdoor and Bus byte enables computation issue?

    By jordan,   
    • 3 replies
    • 7.1k views

  21. uvm_reg_field W1C/W0S update problem

    By saxmanlogic,   
    • 2 replies
    • 7.8k views

  22. Are there any recommendations/guidelines on using UVM run sub phases?

    By mramdas,   
    • 0 replies
    • 1.7k views

  23. Complicated Register Modeling with uvm_reg

    By Logger,   
    • 0 replies
    • 3.2k views

  24. Why we get SEQREQZMB when jumping to another phase

    By zhiharev,
    • 2 replies
    • 7.3k views

  25. What is a proper way to set fields and update register in uvm register model?

    By timothy,   
    • 1 reply
    • 11.6k views
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