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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

944 topics in this forum

  1. Multiple +uvm_set_severity are ignored

    By ofird,
    • 2 replies
    • 2.9k views

  2. What 's difference between copy and clone?

    By hugemx830202,
    • 3 replies
    • 22.8k views

  3. phase jump to function phases

    By anming,
    • 4 replies
    • 4.1k views

  4. I stink at writing test plans.

    By c4brian,
    • 5 replies
    • 2.2k views

  5. Noob question about how to add configurability to a test.

    By jsan_delis,
    • 1 reply
    • 1k views

  6. how to write more than one register using read and write functions

    By MehulPithva,   
    • 4 replies
    • 2.6k views

  7. Parametrized UVM Verification Environment

    By MarcelA,   
    • 1 reply
    • 2.5k views

  8. DUT Model synchronization

    By c4brian,
    • 4 replies
    • 2.1k views

  9. UVM Monitor Help!!!!

    By Hongnhattl,   
    • 0 replies
    • 1.2k views

  10. SPI-Register Adaptor

    By rsewal,   
    • 1 reply
    • 1.6k views

  11. workaround to control register write order for wide fields

    By ashleywinn,   
    • 1 reply
    • 4.6k views

  12. UVM_VERBOSITY does not affect "[NEWCOMP] Creating" message

    By sharat,
    • 0 replies
    • 1.1k views

  13. deprecated code in uvm

    By uvmcraft,   
    • 5 replies
    • 5.2k views

  14. uvm-systemc

    By fcunha,   
    • 3 replies
    • 1.7k views

  15. UVM_REG post_predict(...) for registers

    By tudor.timi,   
    • 0 replies
    • 2k views

  16. waiting in a sequence

    By ljepson74,   
    • 2 replies
    • 3k views

  17. UVM_DEBUG verbosity level

    By qwerty,
    • 2 replies
    • 7.1k views

  18. Communication in UVM register model

    By zgl5566,   
    • 1 reply
    • 1.5k views

  19. uvm_reg adapter (bus2reg) issue

    By muffadal,   
    • 6 replies
    • 10.4k views

  20. UVM code generates UVM warning for nested register block

    By walkeranderson,
    • 2 replies
    • 2.5k views

  21. multiple functions in uvm_config_db/uvm_resource_db

    By rahulkumarkhokher,
    • 0 replies
    • 991 views

  22. Question about update of mirrored value (RAL)

    By gaurav_brcm,
    • 0 replies
    • 1.1k views

  23. Component model access from both DUT and predictor

    By c4brian,
    • 0 replies
    • 1.1k views

  24. How to pass down configuration objects to non-uvm_component objects like uvm_transaction?

    By kam.zamani,
    • 6 replies
    • 5.2k views

  25. Design of UVM Scoreboard for Single Master Multi Slave ! Best Re-usable Way ??

    By desperado,
    • 3 replies
    • 6.5k views
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