UVM (Pre-IEEE) Methodology and BCL Forum

946 topics in this forum

1. proper layering in an ethernet transaction class

   By c4brian, December 31, 2014   

   • ethernet polymorphism
   • 18 replies
   • 10.4k views
   • 
   • c4brian
   • September 11, 2015

2. UVM Sequence Help

   By marcodemi, September 8, 2015
   • 11 replies
   • 6.4k views
   • 
   • tudor.timi
   • September 10, 2015

3. extracting data from uvm_do_with macro

   By assafgedalia, September 8, 2015
   • 4 replies
   • 2.2k views
   • 
   • assafgedalia
   • September 8, 2015

4. UVM Monitor help!!!

   By Hongnhattl, July 16, 2015   

   • UVM Monitor
   • 21 replies
   • 8.9k views
   • 
   • Hongnhattl
   • September 4, 2015

5. controlled transition from one phase to another

   By anshulgarg, September 1, 2015   

   • uvm
   • phase
   • (and 1 more)

     Tagged with:

     • uvm
     • phase
     • transition of phase
   • 4 replies
   • 1.9k views
   • 
   • bhunter1972
   • September 2, 2015

6. How to set verbosity for uvm_object (not component)?

   By c4brian, September 1, 2015
   • 2 replies
   • 5.1k views
   • 
   • tudor.timi
   • September 1, 2015

7. Am I done testing yet? A (fun!) coverage question..

   By c4brian, August 21, 2015   

   • coverage
   • test plan
   • (and 1 more)

     Tagged with:

     • coverage
     • test plan
     • verification plan
   • 0 replies
   • 1.3k views
   • 
   • c4brian
   • August 21, 2015

8. Multiple +uvm_set_severity are ignored

   By ofird, August 18, 2015
   • 2 replies
   • 3.7k views
   • 
   • ofird
   • August 19, 2015

9. What 's difference between copy and clone?

   By hugemx830202, May 15, 2011
   • 3 replies
   • 23.7k views
   • 
   • nicolbiden
   • August 8, 2015

10. phase jump to function phases

    By anming, July 23, 2015
    • 4 replies
    • 4.7k views
    • 
    • ruchir.bharti
    • August 3, 2015

11. I stink at writing test plans.

    By c4brian, July 28, 2015
    • 5 replies
    • 2.4k views
    • 
    • c4brian
    • July 31, 2015

12. Noob question about how to add configurability to a test.

    By jsan_delis, July 24, 2015
    • 1 reply
    • 1.3k views
    • 
    • c4brian
    • July 28, 2015

13. how to write more than one register using read and write functions

    By MehulPithva, July 21, 2015   

    • register model
    • 4 replies
    • 3k views
    • 
    • MehulPithva
    • July 21, 2015

14. Parametrized UVM Verification Environment

    By MarcelA, August 14, 2013   

    • parameters
    • UVM
    • 1 reply
    • 2.7k views
    • 
    • dflores
    • July 21, 2015

15. DUT Model synchronization

    By c4brian, April 21, 2015
    • 4 replies
    • 2.4k views
    • 
    • c4brian
    • July 20, 2015

16. UVM Monitor Help!!!!

    By Hongnhattl, July 16, 2015   

    • UVM Monitor
    • 0 replies
    • 1.4k views
    • 
    • Hongnhattl
    • July 16, 2015

17. SPI-Register Adaptor

    By rsewal, July 14, 2015   

    • SPI
    • 1 reply
    • 1.8k views
    • 
    • tudor.timi
    • July 14, 2015

18. workaround to control register write order for wide fields

    By ashleywinn, June 26, 2015   

    • uvm_reg_map
    • uvm_reg
    • (and 1 more)

      Tagged with:

      • uvm_reg_map
      • uvm_reg
      • Register Layer
    • 1 reply
    • 5.1k views
    • 
    • uwes
    • June 26, 2015

19. UVM_VERBOSITY does not affect "[NEWCOMP] Creating" message

    By sharat, June 9, 2015
    • 0 replies
    • 1.2k views
    • 
    • sharat
    • June 9, 2015

20. deprecated code in uvm

    By uvmcraft, April 7, 2015   

    • deprecated
    • UVM_NO_DEPRECATED
    • 5 replies
    • 6.1k views
    • 
    • uvmcraft
    • May 26, 2015

21. uvm-systemc

    By fcunha, April 30, 2015   

    • uvm
    • systemc
    • 3 replies
    • 2k views
    • 
    • apfitch
    • May 16, 2015

22. UVM_REG post_predict(...) for registers

    By tudor.timi, May 15, 2015   

    • UVM_REG
    • 0 replies
    • 2.3k views
    • 
    • tudor.timi
    • May 15, 2015

23. waiting in a sequence

    By ljepson74, March 21, 2015   

    • sequence
    • event
    • (and 1 more)

      Tagged with:

      • sequence
      • event
      • wait
    • 2 replies
    • 3.5k views
    • 
    • xzcdream
    • May 8, 2015

24. UVM_DEBUG verbosity level

    By qwerty, May 6, 2015
    • 2 replies
    • 7.9k views
    • 
    • tudor.timi
    • May 6, 2015

25. Communication in UVM register model

    By zgl5566, April 24, 2015   

    • UVM RAL
    • 1 reply
    • 1.7k views
    • 
    • uwes
    • April 27, 2015