uvm sequence for slave implementation

[Madhu]

Hello,

 

I'm trying to implement an AXI Slave VIP and have few questions regarding the implementation.

In this case, the DUT is the master. The AXI Slave checks the interface for valid read /write signals and performs a read/write operation from a memory model. It returns back the write response/read data back to the DUT.

 

1. Since this is a slave VIP , do I need a slave sequence which runs forever sending transactions to the driver ? This is similar to the UVM example where the monitor and sequencer are connected by an analysis port and the sequence calls the peek function to check if a valid transaction is available from the monitor. 

 

(OR)

 

2. Can I skip the sequence/sequencer part and just connect my monitor and driver using an analysis port and pass on the observed transaction from the monitor to the driver for further action ?

 

(OR)

 

3. Im thinking of a 3rd alternative of just using the monitor to the observe the interface and drive back the write response/ read data back using the monitor itself and leave the driver empty. 

 

Please let me know your valuable thoughts and suggestions.

 

Thanks,

Madhu 

[tudor.timi]

You listed your alternatives in decreasing order of complexity, i.e. option 1 needs more code than option 2 which needs more code than option 3. The problem is that the more stuff you throw away, the less flexible your whole solution becomes. I'd stick with option 1 because it provides the most controlability and it's not significantly more difficult to implement.

[ruchir.bharti]

 

I'm trying to implement an AXI Slave VIP and have few questions regarding the implementation.

In this case, the DUT is the master. The AXI Slave checks the interface for valid read /write signals and performs a read/write operation from a memory model. It returns back the write response/read data back to the DUT.

 

To my understanding, your system requirement is to have slave model which can :

- receive AXI transaction from DUT/master.

- perform read/write operation to connected memory depending upon type of transaction.

- response back to DUT/Master.

 

if it is, then possible solution is to create transceiver + monitor + config block as slave agent , where :

 

transceiver : convert signal2trasaction and transaction2signal depending upon config.

config : config block will control delays on request-response path and controlling error response.

monitor : will checks the signals protocol and transferred transaction to scoreboard or functional coverage monitor.

 

else 

you need to work hard on creating sequence+sequencer+driver.