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uwes

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uwes last won the day on December 1 2017

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About uwes

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    uwe_simm

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  1. sounds as if the file ahb_bridge.sv is corrupt.
  2. hi, could it be that this is a UVM earlier than UVM-IEEE? if thats the case then you probably hit a known issue. /uwe
  3. uvm-1.0p1 is pre-historic and uvm-1.1-rc* is just slightly younger. please run with a recent uvm version such as uvm-1.2 or uvm-ieee
  4. hi, you are using uvm1.2 with the uvm11 version of the cadence extensions. please choose one of the following 1. use the cadence distributed version in your install 'irun -uvmhome CDNS-1.2 ....' (no need for any other uvm compile/flags ...) 2. you point to the right extensions 'irun -uvmhome ...yourpath... -uvmexthome <cdnsinstall>/tools/methodology/UVM/CDNS-1.2 ....' i also see that you are using a very old version of ius and it is suggested to use a more recent one. /uwe
  5. hi, there are two questions you ask: 1. why is auto_predict=off the default?: normally auto_predict==off is the more versatile mode of operation. it works through a monitor when the real transaction is seen on the bus, it works in passive mode, it works with back-to-back transfers etc. 2. does setting auto-predict after the write help?: simply no. for auto predict to work the driver-sequencer handshake has to wait till the real end of transaction on the bus and it has to be switched on before the read/write operation.
  6. hi, the technical part of the error is that you missed to include the system functions into your command invication (something like -loadvpi, -svlib or similar). nevertheless i would recommend the file a support ticket to have this resolved. /uwe
  7. hello, again - its hard to suggest something if you cannot clarify what you mean with 'kill'. this could a everything from - killing via 'kill -9' on the os level (or via signals to the simulator) - $stop,$finish and friends - via calls to uvm api methods - through phase operations/jumps - through a message causing the simulation to end - through a 'coded' natural end - through an end of event (by "killing" the clock) - through an end caused by external code .... /uwe
  8. hi to answer the question we need to know 'how' your test is 'killed'. what mechanism is used to terminate? /uwe
  9. a rand var which divides by 7 and 17 can be divided by 7*17 (since both are prime). so the constraint should be as simple as x % (7*17) == 0 //uwe
  10. unless you wrap the string/int/bit in a class instance this will not work.
  11. uvm gives you the ability (via vpi) to write using ```uvm_hdl_deposit(string path, value)```
  12. i think this is yet another issue in the register model related to https://accellera.mantishub.io/view.php?id=5446
  13. Version 1.0.0

    59 downloads

    hi, this archive contains the code for a framework to build indirect registers in a flexible fashion. More insight are shown at dvcon2017-us /uwe
  14. sv should be supported too in hal. typically hal is more focused on rtl code. /uwe
  15. there are a few points to add here 1. since this a specific request for a particular tool please raise a request with your vendor 2. fork/disable etc are subject process control and are very close to grey area's of the vlog spec and/or races - so you might see differences in behviour 3. a much better solution than to disable the block are one of the two following: a) recode the for loop to a while loop >for (int k=0; k<64; k++) int k=0; int flag=1; while(k<64 && flag) do k++; .... // set flag to break done or B) wrap the for loop in a task and then terminate the task with a "return" upon the condition instead of a break /uwe
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