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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

946 topics in this forum

  1. UVM code generates UVM warning for nested register block

    By walkeranderson,
    • 2 replies
    • 3k views

  2. multiple functions in uvm_config_db/uvm_resource_db

    By rahulkumarkhokher,
    • 0 replies
    • 1.1k views

  3. Question about update of mirrored value (RAL)

    By gaurav_brcm,
    • 0 replies
    • 1.3k views

  4. Component model access from both DUT and predictor

    By c4brian,
    • 0 replies
    • 1.2k views

  5. How to pass down configuration objects to non-uvm_component objects like uvm_transaction?

    By kam.zamani,
    • 6 replies
    • 6k views

  6. Design of UVM Scoreboard for Single Master Multi Slave ! Best Re-usable Way ??

    By desperado,
    • 3 replies
    • 7k views

  7. Use objections in uvm phase functions? (or just tasks)

    By ljepson74,   
    • 4 replies
    • 9k views

  8. sequence DUT synchronization

    By c4brian,   
    • 18 replies
    • 8.8k views

  9. Multiple threads writing to different fields of a config register

    By horacelau,
    • 3 replies
    • 2.1k views

  10. UVM analogous to VMM's "wait_if_stopped" method

    By Madhu,   
    • 1 reply
    • 1.3k views

  11. Why active agent and passive agent?

    By cliffc,   
    • 4 replies
    • 8.4k views

  12. Lock request always wins arbitration in UVM 1.1d?

    By ssokorac,
    • 4 replies
    • 1.6k views

  13. Can we fire two sequence parallel on a single sequencer

    By vivek2585,   
    • 3 replies
    • 4.5k views

  14. UVM Base Class Library - uvm_agent with uvm_analysis_port?

    By cliffc,   
    • 1 reply
    • 1.5k views

  15. UVM Base Class Library - uvm_monitor with uvm_analysis_port?

    By cliffc,   
    • 0 replies
    • 1.7k views

  16. Should UVM Analysis Interface write const objects

    By allancarter,
    • 11 replies
    • 3.7k views

  17. Configuration of DUT

    By jlnagel,
    • 9 replies
    • 4.8k views

  18. RAL register read through an adaptor

    By lhsaid,
    • 1 reply
    • 2.7k views

  19. constraining sub-sequences in a virtual sequence - best practice?

    By soloist_huaxin,
    • 2 replies
    • 3.6k views

  20. type_id not in scope when deriving an uvm_object

    By jlnagel,
    • 2 replies
    • 5.4k views

  21. null pointer access in uvm_reg::Xcheck_accessX line 2624

    By allancarter,   
    • 2 replies
    • 2.8k views

  22. Could the m_uvm_sched be given up?

    By qinhailiang,
    • 0 replies
    • 1.1k views

  23. verification env for can controller using uvm

    By swathi92,
    • 5 replies
    • 1.6k views

  24. the parent-child relationship of add method of uvm_phase

    By wszhong631,
    • 2 replies
    • 1.4k views

  25. UVM for ESL DUT verification

    By mivan,   
    • 3 replies
    • 3.1k views
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