UVM (Pre-IEEE) Methodology and BCL Forum

944 topics in this forum

1. handle to uvm_component in uvm_object

   By dipling, June 6, 2016   

   • uvm_object
   • uvm_component
   • (and 1 more)

     Tagged with:

     • uvm_object
     • uvm_component
     • handle
   • 1 reply
   • 1.4k views
   • 
   • tdminion
   • June 14, 2016

2. UVM RAL - Register Verification for Different Access types

   By sanket_gajjar, June 1, 2016   

   • Register verification
   • 0 replies
   • 3.3k views
   • 
   • sanket_gajjar
   • June 1, 2016

3. How to use the Memory Allocation Manager

   By Louis, February 17, 2012
   • 2 replies
   • 3.8k views
   • 
   • gaurav_brcm
   • May 26, 2016

4. UVM Read Problems

   By kiranbhaskar, January 26, 2012
   • 12 replies
   • 8.8k views
   • 
   • valuedCustomer
   • May 25, 2016

5. Multiple architectures - which one?

   By ericdecker70, May 19, 2016
   • 0 replies
   • 636 views
   • 
   • ericdecker70
   • May 19, 2016

6. uvm_random_stimulus usage

   By kumarv, January 4, 2013
   • 4 replies
   • 1.6k views
   • 
   • hevangel
   • May 18, 2016

7. Disadvantages of abstract classes instead of virtual interfaces?

   By gbbrown, January 12, 2012
   • 4 replies
   • 7.9k views
   • 
   • apfitch
   • April 28, 2016

8. Why doesn't this virtual interface connection crash and burn

   By mkorpi, April 7, 2016   

   • virtual interface
   • 1 reply
   • 1k views
   • 
   • tudor.timi
   • April 7, 2016

9. multiple interfaces accessing the same uvm_reg

   By sudheerv, April 7, 2016
   • 0 replies
   • 1.2k views
   • 
   • sudheerv
   • April 7, 2016

10. Is this UVM register model bug being address? UVM/RSRC/NOREGEX

    By Logger, March 18, 2016
    • 4 replies
    • 4.2k views
    • 
    • uwes
    • March 23, 2016

11. reset_phase to be obsolete soon ?

    By chitlesh, April 3, 2015   

    • uvm
    • reset_phase
    • (and 1 more)

      Tagged with:

      • uvm
      • reset_phase
      • run_phase
    • 4 replies
    • 2.5k views
    • 
    • Sivasankaran M
    • March 18, 2016

12. Selection of specific physical interface in default UVM register layer sequences

    By nikunjhinsu, January 1, 2016   

    • uvm_reg_map
    • Register Layer
    • (and 6 more)

      Tagged with:

      • uvm_reg_map
      • Register Layer
      • uvm_reg_access_seq
      • uvm_reg_bit_bash_seq
      • APB
      • I2C
      • get_maps
      • uvm_reg_single_access_seq
    • 2 replies
    • 2.5k views
    • 
    • nikunjhinsu
    • February 20, 2016

13. uvm_send is blocked even after driver executes item_done

    By ninad.pachpute, September 19, 2014   

    • uvm
    • sequence
    • (and 1 more)

      Tagged with:

      • uvm
      • sequence
      • uvm_send
    • 8 replies
    • 5.4k views
    • 
    • avinash123
    • February 10, 2016

14. Guideline of using uvm objection

    By ranjisan, February 14, 2011
    • 3 replies
    • 13.6k views
    • 
    • joniale
    • February 9, 2016

15. Calling put_response when sequence that initiated sequence item has terminated

    By walkeranderson, January 13, 2016
    • 1 reply
    • 1.2k views
    • 
    • mastrick
    • January 14, 2016

16. receiving null pointer error when accessing config object from uvm_do_with

    By assafgedalia, January 7, 2016
    • 2 replies
    • 3.7k views
    • 
    • assafgedalia
    • January 7, 2016

17. Uvm filed macro

    By Nikhil, November 20, 2015
    • 2 replies
    • 1.4k views
    • 
    • agnesmary
    • January 7, 2016

18. Virtual Sequencer :: Sequencer Arbitration

    By tinku, January 4, 2016
    • 0 replies
    • 982 views
    • 
    • tinku
    • January 4, 2016

19. OVM RGM Porting to UVM

    By ggupta, April 10, 2013
    • 8 replies
    • 4.1k views
    • 
    • viru_agnisys
    • November 25, 2015

20. (Possible) Bug in uvm_mem

    By tudor.timi, March 13, 2015   

    • UVM RAL
    • issue
    • 3 replies
    • 2.3k views
    • 
    • sanjeevs
    • November 24, 2015

21. UVM Register Model Burst Access

    By cschmitt, April 12, 2012
    • 5 replies
    • 10.8k views
    • 
    • tudor.timi
    • November 23, 2015

22. uvm_reg::write updates regmodel in explicit prediction mode

    By Alex, October 16, 2015
    • 6 replies
    • 11.5k views
    • 
    • sumeetg
    • November 21, 2015

23. Adding a run-time phase example

    By walkeranderson, November 19, 2015
    • 1 reply
    • 1.4k views
    • 
    • walkeranderson
    • November 20, 2015

24. my test stuck in uvm sequence `uvm_send()

    By jakfens, November 18, 2015   

    • li
    • 1 reply
    • 1.5k views
    • 
    • jakfens
    • November 19, 2015

25. Simulation speed/efficiency

    By c4brian, November 3, 2015
    • 7 replies
    • 1.8k views
    • 
    • c4brian
    • November 13, 2015