UVM Register Model Burst Access

[cschmitt]

The UVM testbench I am working on uses an I2C interface to program registers in the DUT. I currently have the register model working for basic reads and writes. However, one of the features in the design allows for burst access to registers. For example, I could send the CTL register address on the I2C bus and then send several bytes of data. The first byte would go to the CTL register, and the design would auto-increment the address so the next byte would go to the next register.

Is there a way to implement this burst access with the register model?

[petermonsson]

Hi,

The UVM RAL system doesn't provide direct burst access. A way to inject burst access is to save the address of the current transaction inside the low level driver and compare this address with the address of the next transaction. For I2C specifically, you'd need to put the item_done(), get_next_item() part right between the ACK/NACK and the potential STOP condition.

I hope this helps

Peter

[jakubdudek]

Hi there,

 

There is an undocumented obscure argument to the uvm_reg::read and write functions called extension which is of type uvm_object.  It defaults to NULL.  While not documented in the class reference manual, the comment in the code stipulates it can be used to for user defined extensions to the read/write calls.

 

I have successfully implemented a burst read using this argument (for a spi protocol agent).  The call is the same (register.read) but i pass the extra extension argument.  I created a class called burst_extension which contains the burst size and a queue of data to be filled from the spi bus (could be used for writes as well) and a burst size.  Assuming you are using a uvm_reg_adapter, the adapter can retrieve the current uvm_reg_item by calling this.get_item() inside the reg2bus routine (can't do it inside bus2reg).  Magically, the reg_item object contains a handle to the extension object   From there I can access the extension which contains the burst size and the data.  I can then translate it appropriately into a burst operation on the bus.

 

From the user's point of view, it is nice because burst calls are simply the read/write calls with an extra argument.  The adapter can get a little messy, but it is one-time pain and abstracted from other users.

 

I'd be happy to provide more details.

-Jakub

[nikhil_guhagarkar]

Hi Jakub

 

Thanks for the splendid explanation.

I would like to know the details

What changes you did in the reg_adapter (code snippet if possible)

Code for your burst_extension and how you used it write doing register.write

 

Thanks a lot in advance.

 

Nikhil

[MehulPithva]

Hi,

I am using uvm standard register model , register adapter (bus2reg & reg2bus) to send and receive transaction to ral model and DUT.
and it is working fine if i do single read and write.(means i perform the 32 bit read n write using reg.read(status,address,data)reg.write(status,address,data))

My challange is that i have to perform the more than 32 bit transaction which performs the read and write on multiple registers,
If there any way to use the same reg.read/write method to perform more than one register

 

 

 

it seems your bus2reg implementation would be helpful , if you can share it

[tudor.timi]

I've written about this topic here: http://blog.verificationgentleman.com/2015/11/accessing-multiple-registers-at-once.html

The post covers both using an extension and an alternative way of doing it.