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sylvainb

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  1. Hi Tudor, Thank you for your answer... I actually found in between a paper that mention this problem (section VII). They also suggest a work-around by using uvm_config_db#(int) instead of uvm_config_db#(hs_type_t), and this works perfectly for me to circumvent the issue!
  2. Hi All, It seems that there is a problem for automatically updating components fields registered with uvm_field_* macros. It works fine if the field is of type int, but it fails if the field is of type enum. Do I miss something? (I tested this code with both UVM 1.1-d and UVM 1.2) class hs_driver extends uvm_driver #(hs_packet); hs_type_t driver_type; int my_param = 10; `uvm_component_utils_begin (hs_driver) `uvm_field_enum (hs_type_t, driver_type, UVM_ALL_ON) `uvm_field_int (my_param, UVM_ALL_ON) `uvm_component_utils_end [...] endclass: hs_drive
  3. Hi Peter, Thank you for you answer. I had indeed a look within the "Linear PCM integrated example test bench". I think the idea of separating the UVC monitor and the coverage by encapsulating the coverage groups within a uvm_subscriber is neat, however I can foresee that the example of the coverage library (lpcm_cov_lib.sv), using only the size as a parameter (16,24 & 32bits), can become easily extremely verbose and clumsy when the numbers of parameters increase and the parameters interact with one another to determine how the cover group should look like. The best of course, would be t
  4. Coverage should sit along with protocol checkers within a UVC states the UVM user guide. In SystemVerilog, it is achieved using covergroup within the monitor, these covergroups are built within the monitor constructor using the 'new()' method - At least it's what is done within the UVC we purchased from a vIP vendor. As a consequence, if I want to make a new derived class for the UVC monitor I am reusing in order to tailor the verification environment to the special needs of my DUT, I am not able to override the initial covergroup within the monitor base class... Is there a better way to pr
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