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bhunter1972 last won the day on August 31 2018
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Tyson reacted to a post in a topic: parsing using system verilog
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Who can provide a summary of what is new and what has changed?
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UVM requires that the sequencer first stop its sequences and then the driver must be certain to not call item_done on any outstanding sequences. To get this working correctly, there's a simple recipe in this paper from a few years ago, and also in the book: http://sunburst-design.com/papers/HunterSNUGSV_UVM_Resets_paper.pdf
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Improving transaction recording
bhunter1972 replied to ambreezesj's topic in UVM SystemVerilog Discussions
Only if recording is enabled for that transaction. To do that, you need to call the enable_recording() function and give it a stream. -
Advanced UVM Textbook Now Available on Amazon
bhunter1972 replied to bhunter1972's topic in UVM Commercial Announcements
I can do even better. You can go here and press Click Inside to look at it yourself: http://tinyurl.com/h7nfgbz -
aditya1vlsi reacted to a post in a topic: Advanced UVM Textbook Now Available on Amazon
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how to use uvm_in_order_comparator
bhunter1972 replied to mrforever's topic in UVM (Pre-IEEE) Methodology and BCL Forum
I find it to be a perfectly reasonable alternative to writing your own comparator. I'm not sure why back in 2012 was considered old. But it does only do one thing. If you need any more advanced comparisons, then it's not that useful. Implementing do_compare in your class is a pretty simple thing to do. Once done, the do_compare provides the ability to create your own custom comparators that can provide more flexibility. -
gaurav_brcm reacted to a post in a topic: Randomization of dynamic arrays
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karandeep963 reacted to a post in a topic: predictor / TLM model paradigm
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predictor / TLM model paradigm
bhunter1972 replied to c4brian's topic in UVM SystemVerilog Discussions
Agree, although I cannot speak for everyone's design or algorithm that they are trying to verify. There are generally two types of predictors: "white models" and "scoreboards." There are plenty of other names for the same things, but generally they boil down to those two. The difference between them is that the former tries to emulate exactly what the RTL does and perform a cycle-by-cycle comparison, whereas the latter sees stimulus input and predicts what the design will do at some point in the future. Of course, there are varying degrees to which these descriptions hold true. For ex -
At Cavium, we hand edited our version of UVM (egads!) to explicitly allow periods. Although, we felt that asterisks and a few others were probably a bad idea. I know I'll probably get hate mail for abusing the standard like that, but we've got chips to make. Here is a patch that you can apply: Index: 1_2/src/base/uvm_resource.svh =================================================================== --- 1_2/src/base/uvm_resource.svh (revision 329382) +++ 1_2/src/base/uvm_resource.svh (working copy) @@ -1412,7 +1412,8 @@ `ifndef UVM_NO_DEPRECATED begin for(int
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Advanced UVM Textbook Now Available on Amazon
bhunter1972 replied to bhunter1972's topic in UVM Commercial Announcements
Come say hi at DVCon 2016 in San Jose on March 2nd at the Real Intent panel! http://dvcon.org/content/event-details?id=199-126 -
bhunter1972 reacted to a post in a topic: When should we use uvm export
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bhunter1972 reacted to a post in a topic: When should we use uvm export
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I've been told that the explanation I have in my book is clear, so I'll just put this here. The diagram in the text helps a lot, but hopefully this will work: When initiating transactions up through a hierarchy, ports can talk to other ports just fine. Imps, though, are always the end of the line. To push transactions down through a hierarchy, TLM provides exports. Exports promote an imp to a higher level in the hierarchy. From another component’s point of view, they look exactly like an imp, but the real imp is buried someplace within the hierarchy. With exports, the external component need
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karandeep963 reacted to a post in a topic: Randomization of dynamic arrays
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Randomization of dynamic arrays
bhunter1972 replied to pushkarkumar's topic in UVM SystemVerilog Discussions
The data array will be created implicitly based on the .size(), if it isn't already created, whenever you randomize the class. However, if you allow the simulator to do this implicitly, then you lose the ability to constrain any of the array's variables, which may or may not be something you care about. If you do, then here's how I do this. First, in my class's new function, I new the array to whatever the largest possible size will be. This is important, and perhaps a little wasteful. Second, I constrain the data.size() as you have above. Third, I can then constrain the data bytes, -
For your specific case, you might consider an alternative frontdoor path. With this method, you create a sequence that runs on--well, any sequencer really--and is assigned to the A & B registers using set_frontdoor. This sequence extends uvm_reg_frontdoor and contains an 'rw_info' variable. This rw_info variable holds the information of the transaction. Based on the value of C, the registers can then be manipulated like any other. Consider: uvm_reg chosen_reg; uvm_reg_status status; chosen_reg = (p_sequencer.reg_block.C.SELECTOR.get() == <A_SELECTED>)? p_sequenc
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c4brian reacted to a post in a topic: good technique to generate a random delay?
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good technique to generate a random delay?
bhunter1972 replied to c4brian's topic in UVM SystemVerilog Discussions
Well, like I said, for brevity's sake I excluded the text from the book. But in short: you can use the wait_next_delay() within a sequence to wait a period of time, or you can embed this delay object in your driver and wait for a number of clocks. Maybe I'm being too idealist, but you never want to tie your sequences to a number of "clocks". Sequences have no notions of clocks or interfaces. Drivers see clocks, sequences see time. There are good reasons for this, but that would be a longer conversation. Your issue with regards to falling off of the clock boundary in your driver is a