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kaushalmodi

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  1. +1 Where do I find all the UVM bug reports? https://accellera.mantishub.io/my_view_page.php seems to be listing only the SystemVerilog workinggroup bugs. Update: I just learned that the UVM Mantis bugs are hidden by default to the public (I wonder why!). You can see them only after you get a 'reporter' level account on the Accellera Mantishub. To do so, send an email to the email address listed in https://www.accellera.org/images/activities/committees/uvm/Reporting_bugs_and_enhancement_requests_for_UVM_2015.pdf to get that "special" access (quoted "special" because I do not u
  2. Here's the same example that can be directly run on EDA Playground: https://www.edaplayground.com/x/4Ydz
  3. Here is a minimal example to reproduce this bug: // Time-stamp: <2019-09-13 08:40:25 kmodi> // Original Author : Kaushal Modi // File Name : begin_time_end_time.sv // Description : Minimal reproducible example to show the issue with // begin_time and end_time of transactions begin of // time type instead of realtime. // Run command : For Cadence: // xrun -uvm -uvmhome CDNS-1.2 begin_time_end_time.sv // Command should be similar for other vendors. // *** Fix is to replace t
  4. Hello all, Today, I ended up in a situation where the transaction boxes in Cadence Simvision will not at the exact time where they were supposed to be. This resulted in a drift of the boxes represented in the waves. On looking closer, the box begin time happened only at 1ns resolution, whereas my agent package's resolution and even the default simulation timescale was 1ns/1ps. So I expected the boxes' begin times to be possible at 1ps resolution (not 1ns). Here are the prints from the uvm_info debug statements in my agent monitor: UVM_INFO @2832.523ns
  5. Here's a minor update with respect to point (1) in my above summary. I had to do: mem_tr = spi_mem_tr::type_id::create(.name("mem_tr"), .contxt(get_full_name())); instead of mem_tr = spi_mem_tr::type_id::create({get_full_name(), ".mem_tr"}); With the latter, I get an SDI/Verilog warning saying: Message! [SDI/Verilog] In sdiT::transactionTypeT ctor, the transaction name had illegal characters. Those characters have been replaced. Here's the new name: 'uvm_test_top_env_spi_m[0]_reg2spi_adapter_mem_tr' ... Message! [
  6. Hi Tudor, Thanks for your immense help. I was finally able to get the overrides work with these changes: (1) Append the full name to the transaction objects generated in the adapter: mem_tr = spi_mem_tr::type_id::create({get_full_name(), ".mem_tr"}); (2) Append the full name even to the adapter object generated in the SPI env: reg2spi_adapter = spi_master_reg_adapter::type_id::create({get_full_name(), ".reg2spi_adapter"}); (3) Finally set the instance overrides as usual in the base test: set_inst_override_by_type ( .relative_inst_path("env.spi_m[0].*"), .original_typ
  7. Thank you. It now makes sense why that full path of "env..." did not work. So I thought that the below would fix that. But it is not.. Below code is in the "SPI env" component whose objects are "spi_m[0]" and "spi_m[1]". reg2spi_adapter = spi_master_reg_adapter::type_id::create(.name("reg2spi_adapter"), .contxt(get_full_name())); `uvm_info("DEBUG_FULL_NAME", $sformatf("Full name of this spi_env obj is %s", this.get_full_name()), UVM_MEDIUM) `uvm_info("DEBUG_FULL_NAME", $sformatf("Full name of the new reg2spi_adapter obj is %s", reg2spi_adapter.get_full_name()), UVM_MEDIUM) Insi
  8. Hi Tudor, Thanks for the reply. I have tried something similar. But that doesn't work. Here's is some code to show what I tried. In the adapter class where I create the transaction objects: mem_tr = spi_mem_tr::type_id::create(.name("mem_tr"), .contxt(get_full_name())); In the base test where I do the overrides: spi_mem_tr::type_id::set_inst_override(.override_type(spi_mem_ext_tr::get_type()) , .inst_path("env.spi_m[0].reg2spi_adapter.*") , .parent(null)); spi_mem_tr::type_id::set_inst_override(.override
  9. Hello, We have a test bench environment where we have 2 objects of the same SPI env class. The SPI env sets the sequencer for the RAL model as follows: reg_model.default_map.set_sequencer(spi_master_agt.mem_sqr, reg2spi_adapter); The transaction type handled by the spi_master_agt.mem_sqr is spi_mem_tr. Now I need to extend the spi_mem_tr to spi_mem_tr_1 and spi_mem_tr_2, and then override spi_mem_tr with those separately for the 2 objects of the SPI env class. // Below does not work set_inst_override_by_type ( .relative_inst_path("env.spi_m[0].*"), // Here spi_m[0] is the fi
  10. As rustagi said, you can extend the uvm_report_server and have your own compose_message function. Here's what I do to have a filename without path and to customize other parts of the message too. class custom_report_server extends uvm_report_server; virtual function string compose_message ( uvm_severity severity, string name, string id, string message, string filename, int line ); // Declare function-internal vars string filename_nopath = ""; uvm_severity_type severity_type = uvm_severity_type'( severity ); begin
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