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apfitch last won the day on August 27 2020
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There's also a video library supplied with Xilinx HLS http://www.wiki.xilinx.com/HLS+Video+Library HLS supports SystemC as well as C++. regards Alan
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Hi Yosri, I don't understand why you want to do this in SystemC, the algorithm you've written just reads from a file and writes to a file, which is well suited to a plain C or C++ program. Some specific comments - you have declared "sig" and haven't used it. In sc_main you've called the SC_METHOD using master.MotionDetector. You don't need to do that, the SC_METHOD is a parallel thread and will run automatically at time 0. However as I said above, my main comment is why are you using SystemC? Why not just write a plain C/C++ program? regards Alan
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There's a complete example here: https://www.doulos.com/knowhow/systemc/faq/#q1 regards Alan P.S. Note it uses inline friends, which is perhaps a bit quirky.
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Philipp A Hartmann reacted to a post in a topic: Clocked thread SC_CTHREAD exclusion during initialization phase
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Clocked thread SC_CTHREAD exclusion during initialization phase
apfitch replied to SystemCInDepth's topic in SystemC Language
Hi Mr SystemCInDepth, I think it's important to realise that SC_CTHREAD is special, in that the specified sensitivity is a clock (the rising or falling edge event of a bool or sc_logic). There's no such thing as a "clock" for SC_METHOD and SC_THREAD - just events on channels such as sc_signal, sc_fifo, or any other channel that implements an event. So I would not say because an SC_METHOD or an SC_THREAD does not have a clock. That's what Philipp meant when he said Does that make it clearer? regards Alan -
Is your sc_fifo a class member? Don't forget you must initialise class members on the constructor initialiser list (at least before c++ 11) regards Alan
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If your goal is to synthesize the design, then your first step should be to check what is synthesisable - are you using a particular high level synthesis tool? Have you checked this it will support sc_fifo and sc_semaphore? If your tool supported std::map, couldn't you use use that? regards Alan
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Difference between Master and Slave Agents
apfitch replied to Shankhadeep's topic in UVM SystemVerilog Discussions
Hi, in UVM people tend to talk about agents as being passive, active, or reactive instead of "master" or "slave". Each agent contains a driver, a monitor, and a sequencer. An active agent has all three. A passive agent monitors, but does not drive. A reactive agent drives, but depends on the DUT more closely (i.e. the agent drives data to the DUT, but reacts in some way with the DUT. So I guess you could be using "master" to mean active, and "slave" to mean reactive *or* passive. regards Alan -
You should be able to view the Call Stack in Visual C++ - that may give you an idea of exactly where the exception is being thrown, regards Alan
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There's lots wrong with your code - did you look at the tutorial on www.doulos.com as someone suggested in the earlier thread? Any way, I've tried to add some comments in your code #include "systemc.h" #include "stdio.h" #include "string.h" #include "stdio.h" #include"stdlib.h" #define _CRT_SECURE_NO_WARNINGS sc_out<bool> in; // DON'T DECLARE A PORT OUTSIDE A MODULE SC_MODULE(synchronous) { bool synchronization() { sc_out<bool> in; // DON'T DECLARE A PORT INSIDE A FUNCTION FILE *workspace = fopen("F:/yo
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Generic payload and custom bytes/words
apfitch replied to Zdenek Prikryl's topic in SystemC TLM (Transaction-level Modeling)
Hi Zdenek, the template parameter to the various sockets represents the width of the bus, so you could change that to 12 from the default of 32. However the existing code does generally assume that 1 byte = 8 bits (e.g. the byte enables work with words split into 8 bit bytes). So you'd probably have to write some custom code, Alan- 2 replies
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Error:<E109> complete binding failed: port not bound:
apfitch replied to ehsanullah's topic in SystemC Language
Hi, the reason for the error is that you're not binding all your ports. You bind the ports in this loop: for(int i=0;i<n;i++) { for (int j=0;j<=i;j++) { std::cout << i << " " << j << " " << std::endl; test_CHOL0->chol_in_data[i][j](chol_in_data[i][j]); test_CHOL0->chol_out_data[i][j](chol_out_data[i][j]); } } but in the second loop you have j <= i. I've added printing and you can see that you only bind 6 of the 9 ports -
I guess first you'd need to add an attribute (extension) to the generic payload to represent the priority. Then you could write a variant of the PEQ which takes into account that priority. regards Alan
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For that kind of modelling you probably need resolved types, e.g. sc_signal_resolved, sc_in/out resolved. These types model signal strength resolution, i.e. if you drive two values such as '1' and 'Z', '1' will be the resulting value because '1' is stronger than 'Z'. Have a look at the SystemC standard 1666-2011, especially section 6.13.5 where there's a little example that might help, regards Alan
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Could you post your code? regards Alan