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  1. Hello, We have programmable registers/tables we would like to randomize. Some of the values are illegal. In real system, the programmgers has to program the registers/tables legal values in legal sequences. We have to make a choice from the following: 1. Constrain values in sequence/configuration so that no illegal condition happens. 2. Set up predictors/scoreboards so that predictors/scoreboards handle appropriately when illegal condition happens. If we choose #1, the constraints may become super-complicated. Also we might mask corner cases we might hit if we have less constraints. If we choose #2, we might hit too many illevant cases that we don't care about, and we may end up missing real corner cases. These are my concerns. Which way is recommended? Thank you for your help!
  2. Hi, We usually use our top level environment in active mode but need to make it work in passive mode. In order to test the top level env in passive mode, I instantiated 2 top level env in the test class. One of them is placed in passive mode and connected to the same DUT that has functional interface and data bus interface. The problem was that it didn't like that both env are using the same root register model name "reg_model". In order to work around, I copied the top level env and modified the passive top level env so that it has a different register model instance name. With this workaround, the passive mode testing worked OK. The monitor works just like active one. Of course, this is not an ideal workaround. Is there a better cleaner way to get around this register model naming issue? Thank you!
  3. Hi Peter, thank you for your response. It is good to know how other companies handle test management. As I organize sequences, it seems that it is easier to manage in a file than multiple files. I think we will not have many sequences if we manage code right. So we decided to stick with a file library for sequences for now. We plan to keep a test class per file for now, but we might consider consolidating test library later. If you don't mind answering my question, do you have multiple configuration objects in your environment? Utilizing configuration files make big difference on test/sequence management. I am considering adding a configuration class which will carry values that will be programmed to registers thru bus interface. Sequences will source the configuration and get the values to be programmed to registers. The values in the configuration will be change in the test class. In this way, we will have less sequences and can customize register test from test class. If you or anyone have comments on configuration management, I appreciate it. Thank you!
  4. Hello, I am wondering if there is any recommendation on how to organize UVM sequence and test class files. Currently we use a single sequence library file and individual test class files. If we use a single library file, the file can gets huge and it is hard to manage with multiple people writing sequences. At the same time, it is nice to be able to see the list of classes in a single file and is easy to copy existing sequence to a new one. I was leaning toward creating a file per class but I would appreciate if you could share your thoughts and experiences with test case management. Thanks!
  5. Hi Kathleen, Thank you for your response. I suppose I should apply the code in the class where print function is getting used? What is the easiest way to apply this to all in the environment? Thank you!
  6. Hello, When I print topology or transactions with arrays, it prints the 1st 5 and the last 5 array elements if the array is big. This is good most of the time. Once in a while, I would like to see the whole array elements. Is there a way to control the size of arrays to be displayed? Thank you!
  7. jadec, maybe I misunderstood about pre-allocation. I removed integer and object array initialization from the item constructor. Then I added function to initialize the size of object arrays in sequence. I have constraint to resize the size of integer dynamic array in the item. There is no problem with this, it creates object and integer array correctly. In the monitor, I added functions to resize object arrays and integer arrays based on configuration. This seems to work fine. I thought I could remove integer array resizing function because pre-allocation is not necessary. That is not the case. Could you clarify what you meant about pre-allocation? Thanks!
  8. Thank you all for response! jadec, thank you so much for your explanation about pre-allocation. I thought I had to initialize any dynamic array in the constructor. I removed logic array size and object array initialization from the constructor and created function in sequence to initialize the object arrays. That seems to work and simulation runs a lot faster. I am doing the resizing in the monitor based on the configuration, that seems to work fine. I also need to collect item without knowing dynamic object array size. I would not know the real size until I collect all data that will be stored to object arrays. In this case, do I have to allocate the maximum possible object array size? Gunther, I use object arrays. It is an array of a class. In my case, I create a class of video line which has dynamic array of video data. I create another class of video frame which has dynamic arrays of line objects. Thank you for the response and help!
  9. I would like to pass configuration object to seq_item when it is created so that dynamic array size defined in the configuration will be used when it is being created. Right now, I am using the maximum size to define the dynamic array size when new function is called and let constraints resize the dynamic arrays in sequence. Sequence passes the configuration to seq_item. In the monitor, the default array size (maximum size) is being used. This works OK but is not a clean way. And the simulation slows down significantly when the maximum size of array is big. I resized dynamic array size in monitor after creation, but simulation is still slow. (Using Cadence simulator.) If dynamic array size bigger than the maximum size is assigned, it does not work. The ideal way is to pass the configuration as input argument when new() function is called but I am not sure if this is allowed in SystemVerilog/UVM. What is the best way to handle this? Thank you for your comments!
  10. I ran an register model example from UVM 1.1 package and have a question about this. This example is at uvm-1.1b/examples/simple/registers/models/coverage. I ran the Makefile.ius after adding coverage option for coverage analysis. Based on the coverage analysis result, coverage results for cg_bits are all 50%. For each coverpoint, there are 4 auto bins. The auto[0] and auto[3] get hit, but auto[1] and auto[2] don't get hit. Is it possible to achieve 100% coverage result with this code below? This is extracted from regmodel.sv under the directory. Thanks! class reg_R extends uvm_reg; rand uvm_reg_field F1; rand uvm_reg_field F2; local uvm_reg_data_t m_current; local uvm_reg_data_t m_data; local uvm_reg_data_t m_be; local bit m_is_read; covergroup cg_bits; wF1_0: coverpoint {m_current[0],m_data[0]} iff (!m_is_read && m_be[0]); wF1_1: coverpoint {m_current[1],m_data[1]} iff (!m_is_read && m_be[0]); wF1_2: coverpoint {m_current[2],m_data[2]} iff (!m_is_read && m_be[0]); wF1_3: coverpoint {m_current[3],m_data[3]} iff (!m_is_read && m_be[0]); wF2_0: coverpoint {m_current[4],m_data[4]} iff (!m_is_read && m_be[0]); wF2_1: coverpoint {m_current[5],m_data[5]} iff (!m_is_read && m_be[0]); wF2_2: coverpoint {m_current[6],m_data[6]} iff (!m_is_read && m_be[0]); wF2_3: coverpoint {m_current[7],m_data[7]} iff (!m_is_read && m_be[0]); endgroup covergroup cg_vals; F1: coverpoint F1.value[3:0]; F2: coverpoint F2.value[3:0]; F1F2: cross F1, F2; endgroup function new(string name = "reg_R"); super.new(name, 8, build_coverage(UVM_CVR_REG_BITS + UVM_CVR_FIELD_VALS)); if (has_coverage(UVM_CVR_REG_BITS)) cg_bits = new(); if (has_coverage(UVM_CVR_FIELD_VALS)) cg_vals = new(); endfunction: new virtual function void build(); F1 = uvm_reg_field::type_id::create("F1",,get_full_name()); F1.configure(this, 4, 0, "RW", 0, 8'h0, 1, 1, 1); F2 = uvm_reg_field::type_id::create("F2",,get_full_name()); F2.configure(this, 4, 4, "RO", 0, 8'h0, 1, 1, 1); endfunction: build `uvm_object_utils(reg_R) virtual function void sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map); if (get_coverage(UVM_CVR_REG_BITS)) begin m_current = get(); m_data = data; m_be = byte_en; m_is_read = is_read; cg_bits.sample(); end endfunction virtual function void sample_values(); super.sample_values(); if (get_coverage(UVM_CVR_FIELD_VALS)) cg_vals.sample(); endfunction endclass : reg_R
  11. Hello Dave, thank you for the response. Sorry, yes, I meant to access a configuration object from an interface instance. I appreciate if you could elaborate how to access configuration object outside of UVM component. One use is to enable/disable check/assertions in interface. Another use is to pass configuration variables used in assertions.
  12. Hello, How can virtual interface access to configuration object? Is there a way to access members of configuration object directly from virtual interface? If not, what is the recommended way to access? Thanks!
  13. Hi Gordon, thank you very much for your response again. 1 & 2: This is my interpretation of your suggestion. If I am wrong, please let me know. I can use something like uvm_component or uvm_subscriber and instantiate all the predictors and scoreboard. This container component should have coverage code and utilize the transactions received from predictors/scoreboard and the register handle to create covergroups. 3: Maybe no need to create multiple register models if register covergroups can be enabled only in register testing and the functional covergroups can be enabled only in functional testing. Can this be done? If so, could you tell me how to do so. Thanks again!
  14. Hi Gordon, Thank you very much for your response and pointer to the paper. I am currently reading the paper, I appreciate it. My environment uses multi-stage predictors to predict the final outputs. The final expected outputs and actual outputs are sent to scoreboard and compared. The predictors get register model handles but scoreboard does not. I have a few questions regarding to your method described here. I hope that I am not asking too much. 1. Do you think your method will work with my environment? If so, how should I do so? If not, what do I need to change? 2. How would you hook up register model with analysis port? 3. My initial plan was to create a register coverage model for register testing, then add functional coverage for functional test. There are so many registers and tables for our design, it is quite cumbersome to do this by hand. So I thought about creating 2 sets of register models, one for register testing, and the other for functional testing. What do you think of this method? Thank you very much!!
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