issue about read write-only register via backdoor

[mrforever]

Hi all,

There is one register model such as this:

class R_r extends uvm_reg;
  uvm_reg_field     vaule;
  ...
endclass : R_r

class A_R_file extends uvm_reg_file;
  R_r     R;
  ...
endclass : A_R_file

 

class R_model extends uvm_reg_block;
  A_R_file     R_f;
  ...
endclass : R_model

 

class my_r_seq extends uvm_reg_sequence;
  R_model regmodel;
  ...
  write_reg(regmodel.R_f.R, status, wdata);
  peek_reg (regmodel.R_f.R, status, rdata);
  ...
endclass : my_r_seq

 

R_r is write-only, when reading R_r via backdoor as above, VCS reports such an error. 

 

 

 

 

UVM_ERROR /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1d/src/reg/uvm_reg_block.svh(2049) @ 406000: reporter [RegModel] Block does not have hdl path defined for abstraction 'RTL'

UVM_ERROR: get: unable to locate hdl path R_f.R

 Either the name is incorrect, or you may not have PLI/ACC visibility to that name

 

The VCS reports that "unable to locate hdl path", but I have used configure() function to configure the hdl path in class A_R_file and class R_model.

 

Did anybody meet the issue?

[sheetal]

Have you tried using the tab file, if you are using VCS.

 

Add rw capability to the memories and the registers you are trying to write using backdoor access, in the tab file as shown below:

 

acc=rw:<MEMORY_NAME>

acc=rw:<hierarchical_path_to_reg_block>

 

Pass this tab file on the vcs command line alongwith the switch:

+applylearn+<tab_file>