UVM register access with multiple masters to same register model

[qwerty 0]

Hi,

We have single register space and 3 masters can accessing that space. 

I want all the masters to access those registers parallely. What can be the best possible way to do it.

Currently, I have to select one at compilation time. 

 

Thanks

 

[Logger 2]

You need to provide more detail.

Like, why do you currently have to select one at compilation time?

What exactly do you mean by parallel access? Do you have 3 separate physical interfaces which can simultaneously access the same register?

Or as often the case, do you have 3 masters which can all access the same registers via a fabric and a single physical interface to the registers?

What are you using for your register model? RAL ( uvm_reg ) ?

[qwerty 0]

yes, i am using uvm_reg. 

There are 3 separate interfaces pcie, spi and i2c which can access same set of registers/memory.

 

Thanks

[Logger 2]

You should use a register model with multiple uvm_reg_maps. One per interface. Assuming you're generating your register model using some sort of tool (rather than by hand), you need to find out how your tool supports that.