Kameshwar Rao Posted September 21, 2016 Report Share Posted September 21, 2016 I have query related to UVM_RAL model. Does it support for case-insensitive for accessing Registers and Register fields items from UVM_RAL model? For example. We have testcase with extension of “cif_test.txt”, so it will more readable format for analog engineers. The contents of testcase looks like as mention below. spi_wr cif CifTestModeControlReg 01210fff --//spi-write cif CifTestModeControlReg ; cif_testmode_test_data=fff; cif_testmode_en=0; cif_testmode_data_sel=0; cif_testmode_skip_pdc=0 Here “ spi_wr indicates command, and cif indicates module_name and CifTestModeControlReg indicates register_name”. while parsing this cif string we use below command. block = model_tb.get_block_by_name(mod_name); --//block is of type uvm_reg_block, dolphin_reg is of type uvm_reg; dolphin_reg = block.get_reg_by_name(reg_name); The above statement of testcase will works fine in functional simulation(Tool used is => Cadence SimVision(64) 14.20-s002). And even same testscripts works fine for Validation environment(I mean after chip tape out) also, currently we are using labveiw programmer Tool. Note – 1 : For the same test cases, few registers are got updated during the validation in labview programmer tool. When we dump this updated test case from labview tool. The test case contents are got updated to capital letters(for example - SPI_WR CIF CIFTESTMODECONTROLREG 01210fff). When this updated testscript want to run on functional simulation is throwing an error related to CIF is not a uvm_reg_block item. Is there any other way which will take care internally (I mean any UVM_RAL api is available which takes care of case-insensitive related to uvm_reg_block and uvm_reg items TYPE). Quote Link to comment Share on other sites More sharing options...
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