In my test sequence, some fields of a register are changed frequently and others are keep previous value.
I wrote the code like below,
register.update(status) // first update
... other code
register.update(status) // second update
The first update was processed but the second update was not seen in the system bus.
I digged into UVM manual and implementation, and found out that 'update' function doesn't update mirrored value.
By change, new_value was same to reset value of fieldY.
So at that time the second update was called, m_mirrored and m_desired were same. That was the reason of no bus transaction.
I tried below codes, and they updated my register properly.
However, they look like strange for me. Why I need to set desired value explicit by getting their internal desired value?
Are my solutions wrong? Are there better ways in this case?