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Hi, I have a top level reg map set up as below. In my adapter I am trying to retrieve all the registers by address of incoming reg_item in bus2reg function to simulate burst condition. The get_reg_by_offset call returns null every time. I don't understand why the address is not found considering all the registers have unique offsets. Infact I retrieved the base address of the incoming reg_item to check if I can the register before incrementing for next offset, but it cannot find the register with base address. Any help is appreciated. Top register file: TOP_map = create_map(.name("TOP_map"), .base_addr('hFE00), .n_bytes(1),.endian(UVM_LITTLE_ENDIAN),.byte_addressing(1) ); default_map = CONTROL_TOP_map; TOP_map.add_submap(this.int_reg_blk.I2C_INT_map, .offset(8'h7C)); TOP_map.add_submap(this.scan_blk.SCAN_CTL_map, .offset(8'h84)); TOP_map.add_submap(this.ctrl_int_reg_blk.HOR_CTRL_map, .offset(8'h94)); TOP_map.I2C_INT_map.add_hdl_path("********", "RTL"); //didn't want to add proprietary code paths get_reg_by_offset call uvm_reg_item in_item = get_item(); base_addr = in_item.map.get_base_addr(); if(!(in_item.map.get_reg_by_offset(base_addr))) `uvm_error(get_type_name(), "Register not found in reg map") else registers[i] = in_item.map.get_reg_by_offset(base_addr+1);
Dear Accellera developers, I have been working with the register model since some weeks. I have tried to understand how the adapters were supposed to be used for all the possible combinations of accesses and register definitions. After those weeks I still have some questions. Lets assume we have a register of 32bits with 3 fields. The databytes per address granularity is 1 databyte per increment of address. In other words, each address increment corresponds to one data byte written . That means that a 32bit register comprises 4 address per register. We have a protocol like AXI that supports byte enable masking. The first field covers only the first data byte of the register. When writing the first field of the register, then our AXI monitor sends one xfer that writes only one byte to the reg_predictor. On the other side, the register predictor that uses the bus2reg function of the adapter, will see that bus access and will try to update the register. I have seen that the UVM library calls bus2reg only once per bus TLM channel transfer. I have seen that the register that outputs bus2reg starts a bus collection process. I have seen that the register update will be done if: 1) the address is inside a register address: if (rw.addr == map_info.addr) begin 2) the bus collector reached the number of bytes needed to complete a register: if (predict_info.addr.num() == map_info.addr.size()) begin I have seen that in case the bus collector doesn´t have all the needed xfers to complete a register (if (predict_info.addr.num() == map_info.addr.size()) begin), a break will stop the loop over the addresses. From the previous information, I guess that the intention with the "write" function of the predictor was, that the monitor provides as many xfers that the collector will always complete all the bytes inside a register. Is that correct? Now come the question with the summary. The write function of the register predictor will be called only once. The bus2reg of the register predictor will be called only once. The collector of the write function in the register predictor will collect only once. The condition: "if (predict_info.addr.num() == map_info.addr.size()" will never be true because the register collected field has a size of 1 byte and the total register has a size of 4 bytes. At least it will not be true until the 4 predict_info addresses are received in the write function. How it is supposed to update fields within the UVM register model? We think we can come around to this problem if we call the write() function for each byte with 3 byte_enables set to zero and one set to 1. Is the monitor supposed to split the 32bit AXI data on the bus into bytes to send those to the register predictor? Could you explain me the concept behind field write and field update of the register model in this context. Are my assumptions and understanding wrong? Any help would be appreciated. Do you have an example for this situation? Looking forward your answer Joachim and Jonathan
Dear all, I'd like to access a register via multiple physical interfaces (bfm). Is it possible to set 2 different sequencers to the registers with same address? I have read this is a known issue from this forum. Could anybody give me a good example? I'm looking for a solution that there is no problem in prediction as well as write/read of UVM_REG. Thanks & Regards,