
gaurav_brcm
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Hi All, I wanted to know the usage of get_hdl_path() and get_full_hdl_path(). Any example would be helpful. I have added set_hdl_path_root for register block on top level and added add_hdl_path for different registers such as : add_hdl_path ('{ '{"RegA", -1 , -1} }); for RegA add_hdl_path ('{ '{"RegB", -1 , -1} }); for RegB And this line in register block : this.set_hdl_path_root("top.dut", "RTL"); Now I want to know what HDL path is getting used while doing peek method ? Thanks, Gaurav
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gaurav_brcm reacted to a post in a topic: Randomization of dynamic arrays
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gaurav_brcm reacted to a post in a topic: walk thru an enumeration
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How to use the Memory Allocation Manager
gaurav_brcm replied to Louis's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi Roman, Is there any documents for this ? I also want to know and use UVM memory manager, but can hardly find any examples and documentation. Thanks, Gaurav -
gaurav_brcm reacted to a post in a topic: SVA for fairness of Round-Robin Arbiter
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UVM Register Field Coverage
gaurav_brcm replied to graeme_jessiman's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi agnesmary, I also had this problem, finally I got reference from Verification Academy forum. Basically after including and setting coverage, you will have to call sample_values from your testbench. Then it will work. -
UVM Register Field Coverage
gaurav_brcm replied to graeme_jessiman's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Hi, I am facing the same problem. Should set_coverage be called only after build_phase ? Thanks. -
Hi, I want to use in-built UVM RAL cover groups. I tried following steps but did not help : 1) Enable coverage building: Before building register model, I use following : uvm_reg::include_coverage("*",UVM_CVR_ALL); 2) To enable sampling : <_regmodel>.set_coverage(UVM_CVR_ALL); In my regmodel there are two types of cover groups: UVM_CVR_ADDR_MAP in top level register model and UVM_CVR_REG_BITS in individual registers. I was hoping that UVM_CVR_ALL would enable sampling of all. I could see cover groups getting built but are not sampled. Am I mi
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Hi, I have following scenario : 1) There are backdoor writes without using RAL to some registers. 2) I want to run reset sequence. Now for this first I want to update mirrored values of registers with backdoor values. Then check those values. What is the method for this ? What is correct way for testing in this scenario ? Thanks.
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Hi All, I am facing an issue: One of the register field is configured as : field_a.configure(this, 12, 17, "RO", 0, 12'h0, 1, 0, 1); field_a.set_compare(UVM_NO_CHECK); While doing a reset test, first I reset model then start test. But test fails with : UVM_ERROR -- value read from DUT (0x0000000080001e00) does not match mirrored value (0x00000000XxxXfe00) Basically the fields declared as RO and UVM_NO_CHECK goes X ? Any idea what I am missing or doing wrong ? Thanks.
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gaurav_brcm reacted to a post in a topic: How to change the print format used by UVM?
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Waiting for clocks in sequence
gaurav_brcm replied to gaurav_brcm's topic in UVM (Pre-IEEE) Methodology and BCL Forum
Thanks for pointing the link . Helps a lot. Regards, GG -
Hi All, This may seem to be a basic question. But I need to know methodology and correct way of doing it. If I have to wait for some clocks in sequence , how do we achieve it ? 1) In driver , we have interface handle so there we can wait and use uvm_event ?? 2) Use #delays in sequence . Please let me know the correct method. Thanks, GG