gaurav_brcm

Hi agnesmary, I also had this problem, finally I got reference from Verification Academy forum. Basically after including and setting coverage, you will have to call sample_values from your testbench. Then it will work.

Hi, I am facing the same problem. Should set_coverage be called only after build_phase ? Thanks.

Hi Uwes, Thanks for your reply. Yes it is just printing problem. - Gaurav

No I have fields defined between 28 to 31 and thats what amazes me. These are defined as : field_b.configure(this, 1, 31, "RW", 0, 1'h1, 1, 1, 1) field_c.configure(this, 2, 29, "RW", 0, 2'h0, 1, 1, 1) So X should not in bit 29 , 30 , 31.

Actually there is one problem here : Though only [28:17] are set for UVM_NO_CHECK, mirrored value extends it till 31 , which is wrong. Thanks, Gaurav

Thanks a lot for your reply Tudor. Helps a lot.

Hi All, I am facing an issue: One of the register field is configured as : field_a.configure(this, 12, 17, "RO", 0, 12'h0, 1, 0, 1); field_a.set_compare(UVM_NO_CHECK); While doing a reset test, first I reset model then start test. But test fails with : UVM_ERROR -- value read from DUT (0x0000000080001e00) does not match mirrored value (0x00000000XxxXfe00) Basically the fields declared as RO and UVM_NO_CHECK goes X ? Any idea what I am missing or doing wrong ? Thanks.