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Showing results for tags 'override'.
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UVM Override V/s Simulator Compile/Elab
karandeep963 posted a topic in UVM SystemVerilog Discussions
Hi Folks, Interestingly today making some tweaks I faced a scenario with overrides. Suppose I add some variables in the extended class which are not present in the base class. Then I called the uvm_set_type_override from my top test. Interestingly I wanted to access those newly added variables in final_phase of some component , but during the simulator compile/elaboration phase it fails since the overrides are active during Simulation run-UVM_BUILD_PHASE. So my question is , if someone using some legacy code and wanted to update the stuff without re-writing again/or m -
Hello, We have a test bench environment where we have 2 objects of the same SPI env class. The SPI env sets the sequencer for the RAL model as follows: reg_model.default_map.set_sequencer(spi_master_agt.mem_sqr, reg2spi_adapter); The transaction type handled by the spi_master_agt.mem_sqr is spi_mem_tr. Now I need to extend the spi_mem_tr to spi_mem_tr_1 and spi_mem_tr_2, and then override spi_mem_tr with those separately for the 2 objects of the SPI env class. // Below does not work set_inst_override_by_type ( .relative_inst_path("env.spi_m[0].*"), // Here spi_m[0] is the fi -
Is there any way in which we could override the run_test function from the "uvm_root" class .. ? The reason i am asking this is that .. when i pass the test name via +UVM_TESTNAME="test1" I could like the run_test to run the test "test1" or some other test based on a different command line option .. E.g. If is send +UVM_TESTNAME="test1" ... run_test should run "test1" but if i send +UVM_TESTNAME="test1" +override_test , run_test should run "test2"... so basically in the run_test() task I could like to have something as below : test_override = uvm_cmdline_proc.get_ar
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Following is the example class my_sequence extends uvm_sequence... string file_name; `uvm_object_utils_begin(mysequence) `uvm_field_string(file_name,UVM_DEFAULT) `uvm_object_utils_end endclass class basic_test extends from uvm_test function build_phase(..) set_config_string("*", "file_name", abc.txt); endfunction endclass.. I am passing file_name(abc.txt) from test with set_config_string, but, it is not taking effect. I did the same thing in driver. it worked well. does UVM supports, overriding local variables in sequence. Please let me know... -
What is the easiest way to get my simulation to die upon reaching the first UVM_ERROR? (I suppose the reporting class could be extended and overridden, or something like that, but if it gets too complicated (as this is not smthg I expect to do much), I'll just temporarily change the offending statements to `uvm_fatals....which is what I just did.) Is there a built-in switch or define that I can override at the command line? -
I am trying to recreate/understand a testbench problem I currently have by creating a small example. In creating that small example, I am running into a problem. Below, in the "try1" and "try2" lines, I am attempting to override apple with orange. Can anyone tell me what I am doing incorrectly? package my_pkg; import uvm_pkg::*; `include "uvm_macros.svh" class orange extends uvm_component; `uvm_component_utils(orange) function new(string name, uvm_component parent); super.new(name,parent); endfunction : new task run_phase (uvm_phase phase); `uvm_info("UVC"
