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Hi all, I have a couple of counters in my monitor's run_phase which I'm trying to print in the report_phase. But, the test itself is being killed (I cannot edit the file which is killing the test) which my monitor is still in the run_phase & hence the counters aren't being printed. Is there any way to enforce the report_phase to be run/ any way to call the report_phase from within the monitor file ?

The cook book from Mentor tells following and in another thread, the moderator also suggested against using the sub phases of run. However in one of my projects, I do find the need for using them (and infact we had an internal implemention of something similar in our previous OVM version). Are there any thing happening on this front? Is there a risk in using the sub phases if some of that changes in a future version? "The Accellera UVM committee is still developing the use models and APIs for new UVM phasing as it relates to sequences and transactors. In the mean time, our recommendation is to wait until that work is done and the API is stable. There are a number of future articles in this section which will be available here at that time, and which will describe our recommendations for using this technology. These include: How to make your testbench phase aware [Not yet available] How to manage sequences in the context of phasing [Not yet available] How to design reusable transactors that work in the context of phasing [Not yet available] "

Hello there, As per Mentor's UVM guidelines 5.2 [1], reset_phase() will be obsolete in future releases. During DVCon 2014, Cadence recommends to use run_phases() on slide 5 of [2]. With the release of UVM-1.2, I believed that the sub-phases of run_phase are now stable and clean. Now with the recommendations above, it seems that the it's better to stick with run_phase() itself. As UVM delelopers, what are your views about it ? What do you recommend ? My intention is not to start a flame war of any kind. But to understand which route to opt in order that most of my UVM code would be compatible with UVM 1.3. All in all, it appears that there is a miscommunication on the web. [1]: https://verificationacademy.com/cookbook/UVM/Guidelines [2]: http://proceedings.dvcon-europe.org/2014/presentations_and_papers/T5_3_presentation.pdf regards, Chitlesh

I am trying to run a couple of test cases using script.But I am getting an error message after running the first test case.This stops the simulation.I am attaching the LOG with this mail.I don't understand why this is happening. I checked previous posts and added +UVM_OBJECTION_TRACE in the vsim command.But I am not able to find out the cause of the error.Can anybody help me?? # UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_test_top raised 1 objection(s): count=1 total=1 # UVM_INFO @ 0: run [OBJTN_TRC] Object uvm_top added 1 objection(s) to its total (raised from source object uvm_test_top): count=0 total=1 # AT TIME=0,APB MASTER IN RESET MODE # AT TIME=1200000,APB MASTER IN ACTIVE MODE # AT TIME=45400000,*************************** EXPECTED_DATA=1792474624,RECEIVED DATA=1792474624 # AT TIME=186600000,*************************** EXPECTED_DATA=222,RECEIVED DATA=222 # AT TIME=231800000,*************************** EXPECTED_DATA=1504340502,RECEIVED DATA=1504340502 # AT TIME=349000000,*************************** EXPECTED_DATA=2367782205,RECEIVED DATA=2367782205 # UVM_INFO Test_Cases/my_test.sv(40) @ 349000000: uvm_test_top [root objections] # The total objection count is 1 # --------------------------------------------------------- # Source Total # Count Count Object # --------------------------------------------------------- # 0 1 uvm_top # 1 1 uvm_test_top # --------------------------------------------------------- # # UVM_INFO Test_Cases/my_test.sv(43) @ 349000000: uvm_test_top [my_component objections] # The total objection count is 1 # --------------------------------------------------------- # Source Total # Count Count Object # --------------------------------------------------------- # 1 1 uvm_test_top # --------------------------------------------------------- # # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_test_top dropped 1 objection(s): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_test_top all_dropped 1 objection(s): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (dropped from source object uvm_test_top): count=0 total=0 # UVM_INFO @ 349000000: run [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (all_dropped from source object uvm_test_top): count=0 total=0 # UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1268) @ 349000000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase # # --- UVM Report Summary --- # # ** Report counts by severity # UVM_INFO : 12 # UVM_WARNING : 0 # UVM_ERROR : 0 # UVM_FATAL : 0 # ** Report counts by id # [OBJTN_TRC] 6 # [Questa UVM] 2 # [RNTST] 1 # [TEST_DONE] 1 # [my_component objections] 1 # [root objections] 1 # ** Note: $finish : C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430) # Time: 349 us Iteration: 68 Instance: /my_top # 1 # Break in Task uvm_pkg/uvm_root::run_test at C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430 # Simulation Breakpoint: 1 # Break in Task uvm_pkg/uvm_root::run_test at C:/questasim_10.2c/win32/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430 # MACRO ./run_do PAUSED at line 18

Q1) Is there truth to the hearsay that the Technical Committee (UVM Working Group) will/might remove run_phase's twelve sub phases (pre_reset, reset, etc.)? If so, when might we expect it? Q2) When is UVM 1.2 expected? Q3) I am just looking into precompiling the uvm base class for our testbenches. (I suppose that I would need two versions, one with -linedebug and one w/o.) Does anyone have any comments about pre-compiling the UVM base class as I now work thru an example?