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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. uvm_do_with constrain problem with sequence

    By kansagaratushar,   
    • 4 replies
    • 5.1k views

  2. Interface Modport and bind: How to get them working

    By justrajdeep,   
    • 0 replies
    • 4.7k views

  3. wait for 'delay' cycles

    By antwens,
    • 1 reply
    • 12.3k views

  4. Processor Verification

    By Naresh Raghava R,   
    • 0 replies
    • 1.4k views

  5. Runtime Fatal Error : p_sequencer can't be casting from a parameterized sequencer

    By caowangyang,   
    • 1 reply
    • 5.1k views

  6. How to run sample test project in model sim for UVM..?

    By George_Ananth,
    • 2 replies
    • 5.4k views

  7. simple override example - with error

    By ljepson74,   
    • 6 replies
    • 22.7k views

  8. UVM sequence library

    By eyafe,   
    • 2 replies
    • 4.8k views

  9. Resetting a randc permutation sequence

    By ljepson74,   
    • 0 replies
    • 4.3k views

  10. default input values for interfaces (for no-connects). to avoid warnings

    By ljepson74,   
    • 3 replies
    • 13.4k views

  11. set register model to several agent

    By gpakillsme,
    • 1 reply
    • 1.7k views

  12. Analysis port that in dynamic array

    By gpakillsme,
    • 2 replies
    • 7.2k views

  13. SystemVerilog DPI

    By bennymao,   
    • 2 replies
    • 3k views

  14. TLM transaction w/o a transaction type? (or w/ simple transaction type, like just "int")

    By ljepson74,   
    • 2 replies
    • 2.3k views

  15. Calling a task in the Agent from my test hangs the test in UVM

    By alih,
    • 0 replies
    • 1.2k views

  16. Passing information between sequence and test

    By alih,
    • 1 reply
    • 4.7k views

  17. ncvlog: *E,EXPENC - Expecting the keyword 'endclass'.

    By ljepson74,   
    • 1 reply
    • 8.9k views

  18. how to (best) delay the start of built-in UVM register test stimulus

    By ljepson74,   
    • 1 reply
    • 4.9k views

  19. How inputs are driven in UVM ?

    By shashank1892,
    • 0 replies
    • 940 views

  20. connect uvm_analysis_export (SV) and tlm_aanalysis_port (SC) with UVMC

    By samng,
    • 3 replies
    • 2.6k views

  21. Register "abc_rm.mem" value read from DUT (0x0000000000000002) does not match mirrored value (0x000000000000000X)

    By KamleshMulchandani,
    • 0 replies
    • 1.4k views

  22. Scoreboarding the Register Model

    By jfevold,
    • 1 reply
    • 1.6k views

  23. Signed field in RAL model

    By bonny,   
    • 0 replies
    • 1.7k views

  24. SV assertion comparing multicycle data bus - specific question

    By ljepson74,   
    • 3 replies
    • 6.1k views

  25. Huge sv file - vcs out of memory

    By seyaleli22,
    • 1 reply
    • 2.3k views
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