UVM SystemVerilog Discussions

596 topics in this forum

1. is it possible to start seqences which run on different clock?

   By gengjie, March 14, 2014
   • 2 replies
   • 1.9k views
   • 
   • David Black
   • March 14, 2014

2. Constraining Sequencer from testcase

   By karandeep963, February 10, 2014
   • 11 replies
   • 11.3k views
   • 
   • nirmish
   • March 14, 2014

3. Polymorphism in testbench

   By amitk3553, February 14, 2014
   • 5 replies
   • 9.1k views
   • 
   • nirmish
   • March 14, 2014

4. Clocking blocking driving very first data half the negedge clock only

   By Mahnedra, March 13, 2014
   • 1 reply
   • 2k views
   • 
   • dave_59
   • March 14, 2014

5. How to make coverage model reusable for multiple port devices?

   By methodman, March 13, 2014
   • 0 replies
   • 1.8k views
   • 
   • methodman
   • March 13, 2014

6. two make errors

   By liya, March 11, 2014   

   • VCS
   • 0 replies
   • 1.8k views
   • 
   • liya
   • March 11, 2014

7. Difference between uvm_hdl_force and uvm_hdl_deposit

   By shreyasraju, February 27, 2014   

   • UVM
   • Force
   • (and 2 more)

     Tagged with:

     • UVM
     • Force
     • System Verilog
     • Deposit
   • 2 replies
   • 16.2k views
   • 
   • David Black
   • February 27, 2014

8. Multithread and automatic variable

   By Parth, February 24, 2014
   • 4 replies
   • 7.7k views
   • 
   • Parth
   • February 27, 2014

9. IP level and SOC level Verification

   By amitk3553, February 27, 2014
   • 0 replies
   • 2.1k views
   • 
   • amitk3553
   • February 27, 2014

10. When a phase completes, are any lingering processes terminated?

    By ljepson74, February 26, 2014   

    • uvm_phase
    • process
    • (and 2 more)

      Tagged with:

      • uvm_phase
      • process
      • end
      • terminate
    • 2 replies
    • 5k views
    • 
    • ljepson74
    • February 26, 2014

11. How to use UVM Sequencer with e-based driver

    By karandeep963, February 18, 2014   

    • edriver
    • uvm sequencer
    • 1 reply
    • 1.2k views
    • 
    • gabi
    • February 19, 2014

12. 8b10b function

    By rlanier, February 17, 2014
    • 0 replies
    • 1.2k views
    • 
    • rlanier
    • February 17, 2014

13. Functional Coverage: How to sample RTL signals in a hierarchy (gives error)

    By alih, February 13, 2014   

    • Functional coverage
    • 1 reply
    • 5.6k views
    • 
    • apfitch
    • February 13, 2014

14. Event Synchronisation from monitor to driver

    By karandeep963, January 30, 2014   

    • UVM Synchronization
    • Class event synchronization
    • (and 1 more)

      Tagged with:

      • UVM Synchronization
      • Class event synchronization
      • Driver - Monitor event sync
    • 2 replies
    • 2.1k views
    • 
    • karandeep963
    • February 12, 2014

15. Accessing SystemC from SystemVerilog TB

    By thuvm, February 7, 2014
    • 2 replies
    • 1.3k views
    • 
    • David Black
    • February 7, 2014

16. UVM in Questasim

    By Hany Salah, February 4, 2014   

    • uvm
    • Questasim
    • (and 1 more)

      Tagged with:

      • uvm
      • Questasim
      • Systemverilog
    • 2 replies
    • 2.9k views
    • 
    • Hany Salah
    • February 6, 2014

17. transaction concept in UVM

    By amitk3553, January 28, 2014
    • 3 replies
    • 1.4k views
    • 
    • apfitch
    • January 29, 2014

18. configuration object and configuration space in UVM

    By amitk3553, January 23, 2014   

    • UVM
    • 3 replies
    • 2.4k views
    • 
    • apfitch
    • January 28, 2014

19. Inquiry in UVM

    By Hany Salah, December 25, 2013   

    • UVM
    • 2 replies
    • 1.9k views
    • 
    • Hany Salah
    • January 24, 2014

20. Why is different the declaration class handle before and after the super call?

    By qinhailiang, January 23, 2014
    • 2 replies
    • 1.4k views
    • 
    • qinhailiang
    • January 24, 2014

21. Accessing arrays

    By antwens, January 23, 2014
    • 0 replies
    • 1.1k views
    • 
    • antwens
    • January 23, 2014

22. differences b/w ovm and uvm

    By amitk3553, January 21, 2014   

    • UVM and OVM
    • 1 reply
    • 1.2k views
    • 
    • apfitch
    • January 21, 2014

23. constraint solver

    By amitk3553, January 21, 2014   

    • SV
    • 1 reply
    • 3.7k views
    • 
    • apfitch
    • January 21, 2014

24. Type-parameterized class and callback

    By mstarilov, January 20, 2014   

    • class callback parameter
    • 0 replies
    • 2.9k views
    • 
    • mstarilov
    • January 20, 2014

25. VPI fault

    By venkatesh.mushini, January 15, 2014   

    • VPI fault
    • 3 replies
    • 1.5k views
    • 
    • venkatesh.mushini
    • January 17, 2014