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default input values for interfaces (for no-connects). to avoid warnings

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May a module or interface have default 'no-connect'  port connections, for ports that we don't need to connect?


I need to use an interface which is shared between testbenches. I instantiate it a lot and don't use many of the ports (i.e. they can be 'no connects')

Using Cadence irun, I get this warning when I don't connect inputs to the interface:  ncelab: *W,CUVWSI 


With tasks/functions, I can have a default value for an input argument.  Is there anything similar for interfaces (or modules for that matter)?


Rather than creating a bunch of dummy inputs for these ports that are not relevant to me, I'd like to change the interface somehow to clear up the warnings for cases where I don't want to use them.



trying to clean up some warnings,




Note: the interface inputs mentioned are being used for a small piece of internal control logic in the interface.   I suppose someone might suggest using parameterized interfaces.  I don't recall offhand, but believe there is a reason that we are not using a parameterized interface for this.  I'll have to check with the original developer.

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I don't think you can directly do this, but here are a couple of ideas:

1) Create a wrapper interface which has your unused inputs tied off. You would instantiate this wrapper in your wire harness, but then you would have to make sure to pass the actual interface in your agents. I haven't tried this, so don't know if it would work.

2) I use the emacs verilog mode to avoid a bunch of typing. Instantiate your interface with the AUTOINST to create all of the ports. Then use the AUTOWIRE to create wires for all unused ports. These can then be tied off. Or you may want to use the AUTOTEMPLATE if you want to instantiate many of the same interface with the same signals tied off.


EDIT: Well, nevermind: I guess you can do this.  Thanks Dave!  In case you are curious, I found this in section of the LRM.

Edited by nguthrie
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Are you asking about defaults for regular Verilog ports of modules and interfaces, or interface ports of modules and interfaces?

SystemVerilog allows default connections for ports that are not interface ports.

interface itf(input logic clk, logic reset=0);
wire signal;
endinterface // itf

module top;
   bit clk;

   itf i1(clk,); // only clk port connected


Ports that are interfaces cannot be left unconnected.

module DUT(itf i);
  always @(i.signal) ...

i.signal would not exist unless it was connected to an actual interface instance of itf.

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