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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. Range must be bounded by constant expressions

    By ssingh,
    • 1 reply
    • 4.5k views

  2. Calling uvm run_test from a program block instead of a module

    By rkovvuri,
    • 8 replies
    • 6.5k views

  3. using a task of class1 in class2 when both class1 &2 have common base classe

    By manjuja1,
    • 3 replies
    • 1.9k views

  4. printing all the $value$plusargs

    By manjubshetty,
    • 2 replies
    • 3k views

  5. uvm_config_db

    By sanketshah,
    • 5 replies
    • 4.8k views

  6. How to get information from monitor using UVM callback

    By pks,
    • 0 replies
    • 1.5k views

  7. Difference between Sequencer, sequence and transaction ?

    By swapnilm,
    • 6 replies
    • 10.2k views

  8. UVM_DISABLE_AUTO_ITEM_RECORDING defined

    By uvm780,
    • 1 reply
    • 3.4k views

  9. Why use virtual word in declaration of a class?

    By swapnilm,
    • 7 replies
    • 11.4k views

  10. Typo of uvm_port_base

    By lothairz,
    • 1 reply
    • 1.1k views

  11. Modeling DUT registers in Scoreboard?

    By tusshar1.1,
    • 0 replies
    • 1.6k views

  12. Problem about return value of function in SV

    By mrforever,
    • 3 replies
    • 1.6k views

  13. synchronization between monitor and driver within an agent

    By sandip.gaikwad,
    • 5 replies
    • 4k views

  14. class invoke itself

    By chenyong,
    • 4 replies
    • 1.5k views

  15. registering sequence with a particular phase of sequencer

    By ecpratik,
    • 6 replies
    • 12.7k views

  16. uvm_config_db

    By sanketshah,
    • 7 replies
    • 3.3k views

  17. Displaying only UVM_LOW and UVM_HIGH log infos

    By omahesh,
    • 2 replies
    • 16.7k views

  18. solve before with size of dynamic array

    By Robert.g.Liu,
    • 3 replies
    • 13.5k views

  19. Sharing variable between two objects

    By sanketshah,
    • 1 reply
    • 2.6k views

  20. ovm to uvm migration

    By ilannov,
    • 0 replies
    • 988 views

  21. need clarification: for...join_none issue

    By Robert.g.Liu,
    • 8 replies
    • 2.7k views

  22. uvm_reg_fifo issues with set_check_on_read()

    By JayP,
    • 0 replies
    • 3k views

  23. Sending transactions over processor bus...

    By wpiman,
    • 3 replies
    • 2.3k views

  24. Is there a way to pass argument to new()?

    By mwhite_cp,
    • 7 replies
    • 7.5k views

  25. TLM2.0 : How to change the default transaction from uvm_tlm_generic_payload to custom

    By rkovvuri,
    • 0 replies
    • 1.3k views
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