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Signed field in RAL model

bonny

By bonny
in UVM SystemVerilog Discussions

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bonny Member

bonny

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Posted

 Hello All,

 

I have some queries regarding RAL model :

 

(1.) How to declare any particular Register's filed as "signed" in RAL model?

(2.) By default all the register fields in RAL model are "unsigned" or "signed"?

 

If possible please guide me for the same.

 

Thanks,

Bonny G. Vora

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