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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. Array of handles

    By ManMe,
    • 1 reply
    • 9.7k views

  2. Help in run phase() of monitor class in uvm?

    By swapnilm,
    • 0 replies
    • 1.6k views

  3. Help in run phase() of driver class in uvm?

    By swapnilm,
    • 0 replies
    • 1.4k views

  4. Re-use tasks from test library to vseq library

    By Nantha,
    • 2 replies
    • 1.3k views

  5. Unable to call a task using a sequence handle present inside another sequence

    By zafar0070,
    • 4 replies
    • 3.7k views

  6. Specifying hdl_path for backdoor register access

    By satishr,
    • 0 replies
    • 1.5k views

  7. style: X / $isunknown checking:where? bind file,interface,monitor?

    By ljepson74,
    • 0 replies
    • 1.1k views

  8. Backdoor register access

    By satishr,
    • 0 replies
    • 1.2k views

  9. The SystemVerilog LRM is now available at no charge

    By dave_59,
    • 1 reply
    • 2k views

  10. systemc models verification using SV/UVM

    By abhineet2210,
    • 2 replies
    • 2.2k views

  11. Help in providing dynamic array elements to a CRC generation function?

    By swapnilm,
    • 1 reply
    • 1.5k views

  12. Help in uvm_do macro in UVM methodology?

    By swapnilm,
    • 1 reply
    • 3.2k views

  13. systemverilog class extension issue

    By smallnokia,
    • 3 replies
    • 2.5k views

  14. How to include the packets generated by transcation class in a File in systemverilog?

    By swapnilm,
    • 0 replies
    • 882 views

  15. creating parameterized class (virtual interface) using factory

    By adhingra,
    • 6 replies
    • 17.4k views

  16. uvm_reg/uvm_mem create functions

    By jeiler,
    • 1 reply
    • 1.2k views

  17. Task argument used in new thread?

    By der57,
    • 4 replies
    • 4.9k views

  18. No error when uvm_component is created using create method

    By shalsays,
    • 2 replies
    • 2.2k views

  19. passing "this" as an argument to a function

    By phil,
    • 4 replies
    • 6.8k views

  20. Expected files after coverage is enabled

    By himan,
    • 1 reply
    • 1.1k views

  21. assign bit type to logic type

    By ssingh,
    • 1 reply
    • 2.4k views

  22. generate unique elements in an array

    By ssingh,
    • 1 reply
    • 5.6k views

  23. having a sequence wait on a value in the driver

    By ljepson74,
    • 2 replies
    • 5k views

  24. forntdoor read failing after backdoor write to a register model while other seq works

    By rsbange,
    • 0 replies
    • 1.7k views

  25. UVM_REG:: How can we use multiple bfm drivers to same regmap using uvm registers

    By tinku,
    • 0 replies
    • 860 views
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