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Interface Modport and bind: How to get them working

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In System Verilog the recommended approach to create interfaces is through modport


suppose I have an interface like 


interface axi_if(input clk, input rst);
  logic arlen;

  clocking mclk@(posedge clk);
    output arlen;

  modport Master(clocking mclk, input clk, input rst);




In Bind we can bind a module to an interface if all the ports are in the portlist.

So is there someway I can bind arlen though it is not defined in the interface port list?

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