caowangyang Posted December 24, 2013 Report Share Posted December 24, 2013 Hi, Dear All, I have a very interesting problem here, image a multiple lanes (changeable) communication system, since some relationship maybe exist across those lanes, in order to model it, I just use a parameterized driver/sequencer in a verification environment, which looks like as: class driver #(parameter LANES = 4) extends uvm_driver #(transaction #(LANES)); class sequencer #(parameter LANES = 4) extends uvm_sequencer #(transaction #(LANES)); Simultaneously, I want to use following Macro in my sequence providing a handle pointed to the sequencer, as we know, called p_sequencer. class pma_base_sequence #(parameter LANES = 4) extends uvm_sequence; `uvm_declare_p_sequencer(sequencer #(LANES)) However, I got following runtime uvm_fatal error: UVM_FATAL ../src/uvc/PMA/pma_sequence_lib.sv(15) @ 0: uvm_test_top.pma_agt.pma_seqr@@pma_base_seq [DCLPSQ] testbench_top.pma_base_sequence.m_set_p_sequencer uvm est_top.pma_agt.pma_seqr.pma_base_seq Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer It looks like the casting from my parameterized sequencer above to specific p_sequencer failed, i.e. this statement failed: $cast(p_sequencer, sequencer#(LANES)) I have no idea what's going on here, does anyone knew it ? I really appreciate if you can help me, thanks in advance ! Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.