alih Posted October 10, 2013 Report Share Posted October 10, 2013 Hello, I have recently started using UVM with System Verilog. I need your help to resolve one of the problems I am facing. My test starts a sequence on a sequencer. In the sequence I am randomizing the address (among other variables). I want to pass the address that has been generated back to the test that started the sequence. The test will use this address value to call execute a task in another agent. I am not sure how do I pass this address back to the test from the sequence. I don't want to hard-code the address. I thought of using the set_config_int() call in the sequence and doing a get_config_int() call in the test but that won't work as both will be executed in the "Run" phase and so can't determine whether the set_config will be called before the get_config. Thanks. Annossyenudge 1 Quote Link to comment Share on other sites More sharing options...
Logger Posted October 11, 2013 Report Share Posted October 11, 2013 You could add an event to the sequence's events pool. Once you've randomized the sequence_item in the sequence, trigger the event passing the sequence_item as the parameter. The test can then wait on that event, and get the sequence_item to get at the address. edit: If this is a pre-existing sequence, that you don't want to modify, extend it instead. You can put the event trigger in the mid_do() or post_do() methods, which ever is appropriate. Quote Link to comment Share on other sites More sharing options...
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