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  1. Thanks to both of you for your answers. Dave, can you provide me with an example of full implementation of your solution? Thanks for your help. Cheers
  2. a usual way to do it is to create a wrapper object and push the wrapper into config_db. Then get this wrapper object from config_db and assign it to the virtual interface pointer (not mentioning the details here) Creating the virtual interface container wrapper parameterized to the strongly typed interface helps here. but in the uvm component, a pointer needs to be created for the parameterised interface. If not wanting the classes to be parameterized, how the virtual interface handle can be created without specifying the parameter as either a default parameter in base class or overri
  3. may I know how the ap aray created in build_phase can be accessed later. uvm_analysis_port #(req_trans) ap_a[]; function void build_phase (uvm_phase phase); .. .. for(int i = 0; i < num_of_agents; i++) begin $sformat(inst_name, "req_agent[%0d]", i); m_req_agent = req_agent::type_id::create(inst_name, this); ap_a = new($sformatf("ap_a[%0d]",i), this); end function void connect_phase (uvm_phase phase); for(int i = 0; i < num_of_agents; i++) begin m_req_agent.ap_a.connect(this.ap_a); end endfunction
  4. a simple question on wait, in driver run task, want to wait for item.delay clock cycles before moving on, may I know below ways are both good, repeat(<item>.delay) @ (posedge clk) assert <signal> or ## (item.delay) thanks
  5. UVM agents use uvm_resource_db/uvm_config_db to configure components. what is the difference between these two?.. how does the below code work, uvm_resource_db # (virtual bus_if.monitor)::read_by_name("interfaces", bus_if_monitor", m_env.m_bus_mon.mi) uvm_config_db#(int)::set(this, "env.*","m_reg_state", venv::START)
  6. May I know what is the difference between a sequencer and sequence driver, are they the same or sequence driver is simply the UVM driver?
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