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Found 7 results

  1. I have recently started using SystemC for my project. I would appreciate if someone could help me with following problem. How can I select part of input port in SystemC? In Verilog it can be done easily by choosing the required bits, e.g., inputPort[3:1] How can I do this in Systemc? I have defined an input port as follows sc_in < sc_int<5> > inputPort; What is the syntax to read bits e.g., [1:3] from inputPort like I did in Verilog? I tried few syntax like inputPort.read({1:3}) but no success.
  2. Hello All I am trying to list out all the ports, sockets in a given SystemC platform. For that I am traversing the hierarchy using sc_get_top_level_object/get_child_object and able to list out all the ports and sockets. But for TLM 2 sockets I get two entries there for example - top_inst.init_inst.initiator_socket - top_inst.init_inst.initiator_socket_export_0 and - top_inst.memory_inst.target_socket - top_inst.memory_inst.target_socket_port_0 It is obvious because each TLM2 socket internally have one port and one sc_export.
  3. HI, What is the purpose of the element, ARRAYS present in component IPXACT definition. In the above image, the port has name: defining physical port name, direction: wire direction, vectors: msb and lsb of the port. What I don't understand is the purpose of arrays here. What it implies? Is it kind of multi dimensional port definition. If so, don't we already have indices, index defining them? Thanks in advance, Bhargav K
  4. Hi, I was trying to map port from a outer module to an input port of inner module. The ports to be mapped in a certain way that a range of input port of outer module is to be mapped with the input port of the inner module. Example is given below. inner module : SC_MODULE(alu) { sc_in<sc_uint<8> > a_in; sc_in<sc_uint<8> > b_in; sc_in<sc_bv<2> > op; sc_in<bool> en; sc_out<sc_uint<8> > out_sig; void calc_out(); SC_CTOR(alu){ cout<<"alu constructor"<<endl; SC_METHOD( calc_out ); sensitiv
  5. Hi all, I have been trying to do something that I'm not sure it's possible. I have some TDF modules that are connected to each other by sca_in and sca_out ports. All of this modules will have at least one of each in/out ports. My idea was that maybe some of them will have some extra in/out ports. For example, if I want two TDFs outputs to go to one TDF input, it is not possible using just one port. Instead, those TDF modules would have a vector of sca_in's so, if I need an extra port, this will be initialized and bound to a signal. All this is already done and compiling. My problem is
  6. May a module or interface have default 'no-connect' port connections, for ports that we don't need to connect? I need to use an interface which is shared between testbenches. I instantiate it a lot and don't use many of the ports (i.e. they can be 'no connects') Using Cadence irun, I get this warning when I don't connect inputs to the interface: ncelab: *W,CUVWSI With tasks/functions, I can have a default value for an input argument. Is there anything similar for interfaces (or modules for that matter)? Rather than creating a bunch of dummy inputs for these ports that are not
  7. Hi, experts, There is several drivers and one subscriber. I put one uvm_analysis_port in each driver and several imps in the subscriber via using macro `uvm_analysis_imp_decl(_a), `uvm_analysis_imp_decl(_b, etc. Also Implement functions write_a(), write_b(), etc. write_a() and write_b() have different processing logic. Then, the uvm_analysis_port in each driver invokes one of the functions write_a(), write_b(), etc. But the VCS reports such an error: Could not find member 'write_a' in class 'uvm_analysis_port', at "/EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/tlm1/uvm_analy
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