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To All Design and DV Engineers! Xilinx Vivado 2020.1 Supports UVM 1.2 and many features of Systemverliog. It supports the same in WebPack (Freeware) Version. There are some limitations on side of assertion cover properties but rest it compile complete SV and UVM including constraints and randomization. Learning UVM without hands-on is difficult. I believe this is opportunity for students, engineers and hobbyists to skill up without relying on paid or online tools as now you can run UVM on your system. For getting started, even though there are many UVM generators, I believe the starters need -
I wish to monitor two signals and wish to determine which of the two changes first and then do some work. module tb( input sel1, input sel2 ); //Determining which of the two changes first // if sel1 changed first //do some work //else //do some other work endmodule There are two signals sel1 and sel2 and I wish to monitor which of the following changed first and then do some work. Can someone help me in doing the same. Thank you.
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I have to write a code that can be synthesised in verilog language and it displays a few values. I need to display the read and write data being read/written to some registers using the AHB protocol. I successfully displayed the write data but I am stuck in displaying the read data. Since the read appears after some time, I couldn't find a way to capture and display the read data. Initially I thought of this : @(negedge clk) wait(rdata) $fdisplay(rdata) But there could be multiple non-zero Read transactions. Now i am stuck here : @(negedge clk) //wait for rdata t
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I am new to UVM and SystemVerilog. For an effective debugging, I wanted to log my transactions coming from the DUT to the monitor into a text file. Since monitor converts into the transaction format, it becomes easy to log the transactions from monitor but I could not find a workaround to do this task. Can someone help with a solution to this problem? Currently, i am using the AHB protocol and I need to keep track of those AHB transactions coming from the DUT. I need to record the address, Read/Write, count, Data to be read/written and time stamps.
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Hi, How to handle memories wide 8 bits in my register model when register map is built with 32 bits width? Thank you Kristina -
I am new to Synopsys VCS. I have been trying to simulate the testbench developed in UVM using VCS in command mode (Linux environment). But, I am not able to get the info displays and the output displays. I am have written the makefile using perl scritps. Can soemeone please tell me where I can find the detail example of using the options in my makefile to run it succesfully while viewing the output displays in command mode -
I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help! -
I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!
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Version 2014.02
404 downloads
Fixed few enum type-cast issues. Moved around the file ordering as needed by compilers. Added extra target for Riviera-Pro Fixed few issues in reg_models. Added Makefile targets for all 3 major EDA tools Steps to use ----------- tar xvfz uvm_ref_flow_2014.02.tgz cd run_dir make vcs make qsta make cdn make rvra -
Hi, I'm newbie to SystemC TLM, coming from SystemVerilog UVM world. I would like to model our RTL in SystemC using TLM2.0 to speed up our Software Development process. Our RTL is not memory mapped bus architecture and we would like to use custom transaction class instead of generic payload. Is it possible to do that using TLM2.0? If yes, could you please provide me with an example. Also, I have four TLM ports communicating with each other in the same model. How does one b_transport method works with all four ports? Is it a good idea to make a model in SystemC rather than having
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Does VCSCompiler for SystemVerilog provides support for assertion based system tasks like $assertvacuousoff. I have been compiling my .sv file and getting an UST error. -
Hi, I am diagnosed with ‘Wrist tendinitis’/’tenosynovitis’ due to RSI (Repetitive Strain Injury). Hence I started using speech recognition as much as possible. On windows, controls are 80% accurate and dictation is 50% accurate. With practice, I am trying to use keyboard and voice recognition just the same way a pianist would sing. I think with the wealth of research in speech recognition, it is possible to get a decent accuracy 1. for coding (UVM, systemverilog) as there are predefined set of keywords, classes, functions etc. 2. for GUI tool controls An example of coding: to see -
Mediatek is looking for verification engineers who are users of SV/UVM for their Bangalore center. Engineers in the experience range from 2-12 years can apply. If interested please send mail to ron.mediatek@gmail.com Essential Skills: Should have worked on at least one ASIC tapeout Hands on with SV/OVM/VMM/UVM Should have executed test planning at block/SoC level
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Hello Everyone, Cadence recently released an update to its UVM multi-language (ML) open architecture library. This version 1.4 is available in the Accellera Upload area at: http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ For more information, you can see this blog posted at Cadence.com: http://www.cadence.com/Community/blogs/fv/archive/2014/06/03/updates-from-the-uvm-multi-language-ml-front.aspx?postID=1334799 =Adam "ML" Sherilog -
Hello, The question is SystemVerilog specific, not related to UVM. I was wondering if it is possible to initialize an interface inside an internal module A and further pass it to an another module B, which is at the same level of hierarchy as the module A. interface Inter (input logic clk); logic a; endinterface module A(Inter inter); logic clk; Inter inter(clk); endmodule module B(Inter inter); always_ff @(posedge inter.clk) ..... endmodule module top; A a( .* ); B b( .* ); endmodule Let's assume module A is a master of some Stream interface (like AXI4-Stream), -
transaction counter from waveform file
alfonsoamarco posted a topic in UVM Simulator Specific Issues
Hi All, I am wondering whether there is an add-on tool or post-processing script to count the occurences of a specific transaction form an existing waveform file, something like all reads from this address range or all the burst from a specific peripheral. Thanks in advance for your help. Cheers, Alfonso -
Can anyone here recommend me chapters needed to read in questasim user guide so as to simulate uvm systemverilog environment ,, let's have assumption that I have no knowledge about simulator commands interface ,,, thanks in advance
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Hi In System Verilog the recommended approach to create interfaces is through modport suppose I have an interface like interface axi_if(input clk, input rst); logic arlen; clocking mclk@(posedge clk); output arlen; endclocking modport Master(clocking mclk, input clk, input rst); endinterface In Bind we can bind a module to an interface if all the ports are in the portlist. So is there someway I can bind arlen though it is not defined in the interface port list?-
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Can SystemVerilog "dynamic array" and "C point" be transfered through DPI? Thanks.
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One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer. The new video series is broken up into twelve clips: Introduction Testbench Integration Adapter Predictor & Auto Predict Register Model & Generation IP-XACT Register Model Classes Register API & Sequences Access Policies Frontdoor & Backdoor Predefined Sequences Demonstration You are now registered for success! (sorry, bad pun
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Hi，experts, I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error，but run time error appears. The code is as follows: 1868 //pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}}; // change because of the run time error 1869 if ((`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)) == 0) begin 1870 pcie_item.first_be = {(length % `DW_BYTE_COUNT){1'b1}}; 1871 end 187
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Hi，experts, I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error，but run time error appears. The code is as follows: 1868 //pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}}; // change because of the run time error 1869 if ((`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)) == 0) begin 1870 pcie_item.first_be = {(length % `DW_BYTE_COUNT){1'b1}}; 1871 end 187
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Dear SystemVerilog/UVM User, I've setup a SystemVerilog Meetup in Silicon Valley for people who are interested in hashing over problems they're having or learning new features in a group setting. http://www.meetup.com/SystemVerilog-Social-Club-Silicon-Valley/ I look forward to seeing you there. all the best, Linc Jepson
