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DPI(Direct Programming Interface) is usually for integrating reference model into systemverilog testbench. Now there is matural integration guideline for reference model written in c/cpp. However, with the popularity of other high-level abstraction programming language like Python,Rust, people tend to develop simulation model in their favorite programming language. I am not sure whether it's considered to support more programming language in systemverilog DPI.

Hi all, I got a question regarding RAL. Assuming there are 2 registers A and B whose width are 8 bits and 16 bits respectively and the bus width is 8 as well. The two UVM registers are created by new(name, 8, UVM_NO_COVERAGE) and new(name, 16, UVM_NO_COVERAGE) for defining their own width. Register A and B locate at address 0 and 1-2 as the address is byte aligned. An user defined register map is created uvm_reg_map my_map = create_map("my_map", 0, 1, UVM_LITTLE_ENDIAN, 1); my_map.add_reg(reg_A, 0, "RW"); my_map.add_reg(reg_B, 1, "RW"); After reg_B.write(status, 16'habcd, .path(UVM_FRONTDOOR)), I would expect 2 transactions with 8 bits each appearing on the bus. However, there is only one access of h'cd to address 1. The other one never comes and it ends up throwing an error "There are 1 incomplete register transactions still pending completion" which is caused by a check on outstanding register accesses pending in predictor in check phase. I tried to find out how the original data value in uvm_reg_item gets split in reg2bus() function. It seems correct that the original data in uvm_reg_item is h'abcd and split to h'cd in uvm_reg_bus_op. But again the other part of data does not come. Also tried to search for answer from other places, for instance the same issue here https://verificationacademy.com/forums/uvm/how-handle-registers-are-wider-bus, it didn't help much unfortunately. If you have any clue about this, please leave your comments. Thanks.

To All Design and DV Engineers! Xilinx Vivado 2020.1 Supports UVM 1.2 and many features of Systemverliog. It supports the same in WebPack (Freeware) Version. There are some limitations on side of assertion cover properties but rest it compile complete SV and UVM including constraints and randomization. Learning UVM without hands-on is difficult. I believe this is opportunity for students, engineers and hobbyists to skill up without relying on paid or online tools as now you can run UVM on your system. For getting started, even though there are many UVM generators, I believe the starters need simple easy to use UVM generator tool. I found the ones available online like Easier UVM or UVMF quite difficult to use and even interact with. I developed a open-source tool "tbengy" to generate a UVM TB and Makefile that will readily get you started and will run on Vivado Simulator. You can read the instructions on https://github.com/prasadp4009/tbengy Hope it helps you all!

I wish to monitor two signals and wish to determine which of the two changes first and then do some work. module tb( input sel1, input sel2 ); //Determining which of the two changes first // if sel1 changed first //do some work //else //do some other work endmodule There are two signals sel1 and sel2 and I wish to monitor which of the following changed first and then do some work. Can someone help me in doing the same. Thank you.

I have to write a code that can be synthesised in verilog language and it displays a few values. I need to display the read and write data being read/written to some registers using the AHB protocol. I successfully displayed the write data but I am stuck in displaying the read data. Since the read appears after some time, I couldn't find a way to capture and display the read data. Initially I thought of this : @(negedge clk) wait(rdata) $fdisplay(rdata) But there could be multiple non-zero Read transactions. Now i am stuck here : @(negedge clk) //wait for rdata to change $fdisplay(rdata) I am new to verilog and SystemVerilog. Please help Thank you

I am new to UVM and SystemVerilog. For an effective debugging, I wanted to log my transactions coming from the DUT to the monitor into a text file. Since monitor converts into the transaction format, it becomes easy to log the transactions from monitor but I could not find a workaround to do this task. Can someone help with a solution to this problem? Currently, i am using the AHB protocol and I need to keep track of those AHB transactions coming from the DUT. I need to record the address, Read/Write, count, Data to be read/written and time stamps.

Hi, How to handle memories wide 8 bits in my register model when register map is built with 32 bits width? Thank you Kristina

I am new to Synopsys VCS. I have been trying to simulate the testbench developed in UVM using VCS in command mode (Linux environment). But, I am not able to get the info displays and the output displays. I am have written the makefile using perl scritps. Can soemeone please tell me where I can find the detail example of using the options in my makefile to run it succesfully while viewing the output displays in command mode

I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!

I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!

Hi, I'm newbie to SystemC TLM, coming from SystemVerilog UVM world. I would like to model our RTL in SystemC using TLM2.0 to speed up our Software Development process. Our RTL is not memory mapped bus architecture and we would like to use custom transaction class instead of generic payload. Is it possible to do that using TLM2.0? If yes, could you please provide me with an example. Also, I have four TLM ports communicating with each other in the same model. How does one b_transport method works with all four ports? Is it a good idea to make a model in SystemC rather than having it in SV UVM? Thanks Zubin

Does VCSCompiler for SystemVerilog provides support for assertion based system tasks like $assertvacuousoff. I have been compiling my .sv file and getting an UST error.

Hi, I am diagnosed with ‘Wrist tendinitis’/’tenosynovitis’ due to RSI (Repetitive Strain Injury). Hence I started using speech recognition as much as possible. On windows, controls are 80% accurate and dictation is 50% accurate. With practice, I am trying to use keyboard and voice recognition just the same way a pianist would sing. I think with the wealth of research in speech recognition, it is possible to get a decent accuracy 1. for coding (UVM, systemverilog) as there are predefined set of keywords, classes, functions etc. 2. for GUI tool controls An example of coding: to see in editor "class myenv extends uvm_env;" I would Say: "class" type: myenv Say:"extends uvm_env;" For GUI usage, tool vendors/users could come up with a number of useful features similar to keyboard shortcuts. These features may be implemented both on Windows and Linux platforms. (Hope in few years engineers are able to dictate their code into a tool and debug it too! Also wish there is research on use of various HCIs for EDA) Thanks for reading my request! Regards, Kal Gandikota P.S.: I used windows speech recognition to write this e-mail as I am suffering from wrist pain. Please kindly ignore grammar mistakes.

Mediatek is looking for verification engineers who are users of SV/UVM for their Bangalore center. Engineers in the experience range from 2-12 years can apply. If interested please send mail to ron.mediatek@gmail.com Essential Skills: Should have worked on at least one ASIC tapeout Hands on with SV/OVM/VMM/UVM Should have executed test planning at block/SoC level

Hello Everyone, Cadence recently released an update to its UVM multi-language (ML) open architecture library. This version 1.4 is available in the Accellera Upload area at: http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/ For more information, you can see this blog posted at Cadence.com: http://www.cadence.com/Community/blogs/fv/archive/2014/06/03/updates-from-the-uvm-multi-language-ml-front.aspx?postID=1334799 =Adam "ML" Sherilog

Hello, The question is SystemVerilog specific, not related to UVM. I was wondering if it is possible to initialize an interface inside an internal module A and further pass it to an another module B, which is at the same level of hierarchy as the module A. interface Inter (input logic clk); logic a; endinterface module A(Inter inter); logic clk; Inter inter(clk); endmodule module B(Inter inter); always_ff @(posedge inter.clk) ..... endmodule module top; A a( .* ); B b( .* ); endmodule Let's assume module A is a master of some Stream interface (like AXI4-Stream), B is the slave. The signal clk could be a regular variable inside the Inter, however, clk must be connected to the interface, so it seems logical to me, that it's on the port list, so developer will not forget to provide it. Therefore (port assignment of inter), the inter has to be initialized inside the module A, not in top as it would be done in case of regular interface usage. The code is for synthesis and my compiler doesn't support virtual interfaces. Does it exist any elegant solution for the described issue ? Thanks, Adrian

Hi All, I am wondering whether there is an add-on tool or post-processing script to count the occurences of a specific transaction form an existing waveform file, something like all reads from this address range or all the burst from a specific peripheral. Thanks in advance for your help. Cheers, Alfonso

Can anyone here recommend me chapters needed to read in questasim user guide so as to simulate uvm systemverilog environment ,, let's have assumption that I have no knowledge about simulator commands interface ,,, thanks in advance

Hi In System Verilog the recommended approach to create interfaces is through modport suppose I have an interface like interface axi_if(input clk, input rst); logic arlen; clocking mclk@(posedge clk); output arlen; endclocking modport Master(clocking mclk, input clk, input rst); endinterface In Bind we can bind a module to an interface if all the ports are in the portlist. So is there someway I can bind arlen though it is not defined in the interface port list?

Can SystemVerilog "dynamic array" and "C point" be transfered through DPI? Thanks.

One aspect that was not covered in the UVM Basics series posted by Cadence in May 2012 was the register layer (aka UVM_REG). In this new video series we are giving an overview of the concepts, components and applications of the UVM register layer. The new video series is broken up into twelve clips: Introduction Testbench Integration Adapter Predictor & Auto Predict Register Model & Generation IP-XACT Register Model Classes Register API & Sequences Access Policies Frontdoor & Backdoor Predefined Sequences Demonstration You are now registered for success! (sorry, bad pun. ) =Adam Sherilog, Cadence

Hi，experts, I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error，but run time error appears. The code is as follows: 1868 //pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}}; // change because of the run time error 1869 if ((`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)) == 0) begin 1870 pcie_item.first_be = {(length % `DW_BYTE_COUNT){1'b1}}; 1871 end 1872 else begin 1873 pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}}; 1874 end `DW_BYTE_COUNT=4; `FDW_BE_WIDTH=4, length is one bit_stream type variable. line 1868 has been commented, changed to line 1869-1874. The reason why i change it is that there is such a run time error: ../sv/04_ref_model/ref_model.sv, line 1868: ** OTENF: S QOP_CONCAT (S,S) /* {} */ Note: OTENF is an internal error meaning Op_Table Entry Not Found Assertion failed " Note: Set environment variable VCS_REPORT_ALL_OTENF to get all the OPTENF errors." at line 711 in file fun.c An unexpected termination has occurred in /EDA_Tools/synopsys/vcs1209/linux/bin/vcs1 at ../sv/04_ref_model/ref_model.sv, 1730 During Codegen During Pass2 Module vcs_paramclassrepository Module vcs_paramclassrepository --- Stack trace follows: [Thread debugging using libthread_db enabled] [New Thread 0xf7be9bb0 (LWP 24498)] 0xffffe405 in __kernel_vsyscall () Thread 2 (Thread 0xf7be9bb0 (LWP 24498)): #0 0xffffe405 in __kernel_vsyscall () #1 0x00aebb26 in pthread_cond_wait@@GLIBC_2.3.2 () from /lib/tls/libpthread.so.0 #2 0x0aee7e64 in ?? () #3 0x00ae9371 in start_thread () from /lib/tls/libpthread.so.0 #4 0x00a41ffe in clone () from /lib/tls/libc.so.6 Backtrace stopped: Not enough registers or memory available to unwind further Thread 1 (Thread 0xf7fd2700 (LWP 24497)): #0 0xffffe405 in __kernel_vsyscall () #1 0x00a0447b in waitpid () from /lib/tls/libc.so.6 #2 0x009ae349 in do_system () from /lib/tls/libc.so.6 #3 0x009ae6c1 in system () from /lib/tls/libc.so.6 #4 0x00aef78d in system () from /lib/tls/libpthread.so.0 #5 0x0b3bc389 in tracker::StackAnnotator::getGdbOutput(char const*, char const*, char const*) () #6 0x0b3bd677 in tracker::StackAnnotator::dumpProcessStack(unsigned int, char const*, char const*) () #7 0x0b3b29c6 in dumpStackTrace () #8 0x0b3b74e7 in vcsAssertNoReturn () #9 0x08fbbf0d in ?? () #10 0x08fbc1c8 in BuildFUNsForRout () #11 0x0907ff8c in BuildMOPsForRout () #12 0x08f4e069 in ?? () #13 0x08f4f12e in ?? () #14 0x08f52423 in CodeGenC () #15 0x09187f31 in Phase234 () #16 0x08806fba in ?? () #17 0x088214ab in ?? () #18 0x088238ee in DoPass2 () #19 0x0876b5ab in doGAToPass2 () #20 0x0876be7a in c_main () #21 0x09293842 in main () Completed context dump phase location* 'Module' 'Module' CPU time: 33.817 seconds to compile make: *** [comp] Error 255 I have done the error analysis, my concept is that maybe the reason is that the value of `FDW_BE_WIDTH - (length % `DW_BYTE_COUNT) has the possibility of zero. So I add the judge condition about the value of `FDW_BE_WIDTH - (length % `DW_BYTE_COUNT), but it still reports the same error about line 1873. If I comment line 1873, the error disappears. It seems like that the problem has something to do with the action of compiler's analyzing the code. Could any expert give me some information? Thanks in advance.

Hi，experts, I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error，but run time error appears. The code is as follows: 1868 //pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}}; // change because of the run time error 1869 if ((`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)) == 0) begin 1870 pcie_item.first_be = {(length % `DW_BYTE_COUNT){1'b1}}; 1871 end 1872 else begin 1873 pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}}; 1874 end `DW_BYTE_COUNT=4; `FDW_BE_WIDTH=4, length is one bit_stream type variable. line 1868 has been commented, changed to line 1869-1874. The reason why i change it is that there is such a run time error: ../sv/04_ref_model/ref_model.sv, line 1868: ** OTENF: S QOP_CONCAT (S,S) /* {} */ Note: OTENF is an internal error meaning Op_Table Entry Not Found Assertion failed " Note: Set environment variable VCS_REPORT_ALL_OTENF to get all the OPTENF errors." at line 711 in file fun.c An unexpected termination has occurred in /EDA_Tools/synopsys/vcs1209/linux/bin/vcs1 at ../sv/04_ref_model/ref_model.sv, 1730 During Codegen During Pass2 Module vcs_paramclassrepository Module vcs_paramclassrepository --- Stack trace follows: [Thread debugging using libthread_db enabled] [New Thread 0xf7be9bb0 (LWP 24498)] 0xffffe405 in __kernel_vsyscall () Thread 2 (Thread 0xf7be9bb0 (LWP 24498)): #0 0xffffe405 in __kernel_vsyscall () #1 0x00aebb26 in pthread_cond_wait@@GLIBC_2.3.2 () from /lib/tls/libpthread.so.0 #2 0x0aee7e64 in ?? () #3 0x00ae9371 in start_thread () from /lib/tls/libpthread.so.0 #4 0x00a41ffe in clone () from /lib/tls/libc.so.6 Backtrace stopped: Not enough registers or memory available to unwind further Thread 1 (Thread 0xf7fd2700 (LWP 24497)): #0 0xffffe405 in __kernel_vsyscall () #1 0x00a0447b in waitpid () from /lib/tls/libc.so.6 #2 0x009ae349 in do_system () from /lib/tls/libc.so.6 #3 0x009ae6c1 in system () from /lib/tls/libc.so.6 #4 0x00aef78d in system () from /lib/tls/libpthread.so.0 #5 0x0b3bc389 in tracker::StackAnnotator::getGdbOutput(char const*, char const*, char const*) () #6 0x0b3bd677 in tracker::StackAnnotator::dumpProcessStack(unsigned int, char const*, char const*) () #7 0x0b3b29c6 in dumpStackTrace () #8 0x0b3b74e7 in vcsAssertNoReturn () #9 0x08fbbf0d in ?? () #10 0x08fbc1c8 in BuildFUNsForRout () #11 0x0907ff8c in BuildMOPsForRout () #12 0x08f4e069 in ?? () #13 0x08f4f12e in ?? () #14 0x08f52423 in CodeGenC () #15 0x09187f31 in Phase234 () #16 0x08806fba in ?? () #17 0x088214ab in ?? () #18 0x088238ee in DoPass2 () #19 0x0876b5ab in doGAToPass2 () #20 0x0876be7a in c_main () #21 0x09293842 in main () Completed context dump phase location* 'Module' 'Module' CPU time: 33.817 seconds to compile make: *** [comp] Error 255 I have done the error analysis, my concept is that maybe the reason is that the value of `FDW_BE_WIDTH - (length % `DW_BYTE_COUNT) has the possibility of zero. So I add the judge condition about the value of `FDW_BE_WIDTH - (length % `DW_BYTE_COUNT), but it still reports the same error about line 1873. If I comment line 1873, the error disappears. It seems like that the problem has something to do with the action of compiler's analyzing the code. Could any expert give me some information? Thanks in advance.

Dear SystemVerilog/UVM User, I've setup a SystemVerilog Meetup in Silicon Valley for people who are interested in hashing over problems they're having or learning new features in a group setting. http://www.meetup.com/SystemVerilog-Social-Club-Silicon-Valley/ I look forward to seeing you there. all the best, Linc Jepson