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muffadal

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  1. Agree. There is already a mantis on fixing this issue and I am assuming this should be fixed for UVM-1.2 release.
  2. Hi All, After debugging this issue for couple of weeks I figured out the solution to this problem. In my testbench I had a define called UVM_DISABLE_AUTO_ITEM_RECORDING enabled. This define forces the driver to end a sequence through req.end_tr();. If you don't have this line in your driver the do_read task in uvm_reg_map will keep waiting at the bus_req.end_event.wait_on(). I removed this define and it all works now . The annoying part is since this is a SoC level testbench I had to digg into many files before I figured out that one of the files has this define. Thanks, Muffad
  3. Hi Tudor, Thanks for your response. I am running the adapter sequence on a dummy virutal sequencer. Here is the code for the dummy virutal sequencer. ******************************************** Virutal Sequencer ******************************************** class ps_regm_vsequencer extends uvm_sequencer #(dummy_seq_item); `uvm_component_utils(ps_regm_vsequencer) mst_rd_sequencer rd_seqr; mst_wr_sequencer wr_seqr; ps_axi_adapter_sequence adapter_seq; // axi_adapter reg2axi; function new (string name = "pmu
  4. Hello Folks, I am unable to get a response from the vsequencer to my register model sequence. I see that the register model sequence does generate the first transaction and when the response of this transaction comes back to the vsequencer the sequence hangs. I found on couple of forums that setting provides_responses bit to 1 in the adapter class should resolve this issue. However I am still not able to make this work. Here are the steps that I followed to Integrate uvm_reg model in my uvm environment. 1. Generate the uvm_reg model using one iregGen/ralGen script 2. Instanti
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