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  1. I receive an integer from an external API, that is actually a fixed point real value, disguised as int for transport compatibility. I need to convert the integer back into it's fixed point representation. I presume I can convert the int to sc_bv. Then, I would expect sc_fixed to have a constructor accepting a sc_bv, and specify the decimal point place through sc_fixed template. Looking through the source, It seem though that sc_fixed cannot be constructed from a sc_bv. The closest thing I see is the char* constructor (pass bits using sc_bv.to_string() ), but I'm pretty sure that converts a decimal string, not a binary string. In short, is there a simple enough way to convert the bits of an integer (in the form of sc_bv) into a real number (say, float) by specifying the fixed point location in the bit vector?
  2. Hi All, I am trying to schedule interrupt of timer for next time as my current logic only executed interrupt only one time. void call_overflow_interrupt(){ //check overflow //cout<<"\nIn callInterrupts func\n"; if((timer_cntrl &(1<<TIMER_CNTRL_OV))&& timer_val==0xff) { intr1=1; timer_intr_status=ENABLE(timer_intr_status,TIMER_OV_INTR); } else{ cout<<"\ncall_overflow_interrupt is not coming\n"; } } And in SC_CTOR i am registering this process SC_METHOD(call_overflow_interrupt); sensitive<<Event; dont_initialize(); Event.notify(256*20,SC_NS);//count=256(0xFF),clock period=20ns I wrote above code but it is not scheduling the process for next time.How this can be achieved?
  3. You need to separate out stimulus generation from monitoring and checking. #include "systemc.h" SC_MODULE(MultTb){ sc_in<bool> clk; sc_out<int> din1; sc_out<int> din2; sc_in <int> dout; void stim_gen(); SC_CTOR(MultTb){ SC_THREAD(stim_gen); sensitive << clk.pos(); } }; void MultTb::stim_gen(){ wait(); din1 = 10; din2 = 10; wait(); printf("[MON]:: %0d * %0d = %0d\n", din1.read(), din2.read(), dout.read()); din1 = -10; din2 = 10; wait(); printf("[MON]:: %0d * %0d = %0d\n", din1.read(), din2.read(), dout.read()); sc_stop(); }
  4. Hello, I downloaded the latest systemC systemc-2.3.3, compiled and installed it locally. I also ran some of the tests and an example, and it all works fine. This is on RHEL 6.0, using GCC 6.3. During the compile, I got warnings like this: libtool: warning: library '/nis/asic/apps2/linux/sw/verilog/xcelium/XLM_20.09.011/tools.lnx86/cdsgcc/gcc/6.3/install/lib/../lib64/libstdc++.la' was moved. Searching on that warning (or similar) didn't turn up much, and the compile/install all works fine, so I thought it was no big deal. However, this same warning seems to be triggering an error for UVM-SystemC compile. I've downloaded: uvm-systemc-1.0-beta3, and I'm compiling it by pointing to the above newly compiled/installed systemC. ../configure --prefix=/nis/asic/gls_dump/ricardga/uvm-systemc-1.0-beta3 --with-systemc=/nis/asic/gls_dump/ricardga/systemc-2.3.3 --enable-debug --enable-profiling=instrument ------------------------------------------------------------------------------ Configuration summary of UVM-SystemC 1.0-beta3 for x86_64-pc-linux-gnu ------------------------------------------------------------------------------ Directory setup (based on SystemC layout): Installation prefix: /nis/asic/gls_dump/ricardga/uvm-systemc-1.0-beta3 Header files: /nis/asic/gls_dump/ricardga/uvm-systemc-1.0-beta3/include Libraries: /nis/asic/gls_dump/ricardga/uvm-systemc-1.0-beta3/lib Documentation: /nis/asic/gls_dump/ricardga/uvm-systemc-1.0-beta3/docs Examples: /nis/asic/gls_dump/ricardga/uvm-systemc-1.0-beta3/examples Target architecture: linux64 Build settings: Compiler (flags): g++ Preprocessor flags: SystemC CFLAGS: -I/nis/asic/gls_dump/ricardga/systemc-2.3.3/include SystemC LIBS: -L/nis/asic/gls_dump/ricardga/systemc-2.3.3/lib-linux64 -lsystemc Additional LIBS: Enable compiler optimizations: yes Include debug symbols: yes Generate instrumentation calls: instrument Regular expression library: POSIX ------------------------------------------------------------------------------ But then when I call gmake, I'm getting an error that seems related to the warning: > gmake Making all in docs gmake[1]: Entering directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/docs' gmake[1]: Nothing to be done for `all'. gmake[1]: Leaving directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/docs' Making all in src gmake[1]: Entering directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/src' gmake all-recursive gmake[2]: Entering directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/src' Making all in uvmsc gmake[3]: Entering directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/src/uvmsc' gmake[4]: Entering directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/src/uvmsc' CXX base/uvm_component.lo CXX base/uvm_component_name.lo CXX base/uvm_coreservice_t.lo CXX base/uvm_default_coreservice_t.lo CXX base/uvm_event_callback.lo CXX base/uvm_event.lo CXX base/uvm_globals.lo CXX base/uvm_mutex.lo CXX base/uvm_object.lo CXX base/uvm_object_globals.lo CXX base/uvm_root.lo CXX base/uvm_transaction.lo CXX base/uvm_version.lo CXX cb/uvm_callback.lo CXX cb/uvm_callbacks_base.lo CXX cb/uvm_typeid.lo CXX comps/uvm_agent.lo CXX conf/uvm_config_db_options.lo CXX conf/uvm_resource_base.lo CXX conf/uvm_resource_db_options.lo CXX conf/uvm_resource_options.lo CXX conf/uvm_resource_pool.lo CXX dpi/uvm_hdl.lo CXX factory/uvm_default_factory.lo CXX factory/uvm_factory_override.lo CXX misc/uvm_misc.lo CXX misc/uvm_scope_stack.lo CXX misc/uvm_status_container.lo CXX phasing/uvm_bottomup_phase.lo CXX phasing/uvm_common_phases.lo CXX phasing/uvm_domain.lo CXX phasing/uvm_objection.lo CXX phasing/uvm_phase.lo CXX phasing/uvm_process_phase.lo CXX phasing/uvm_runtime_phases.lo [134/1811] CXX phasing/uvm_topdown_phase.lo CXX policy/uvm_comparer.lo CXX policy/uvm_packer.lo CXX policy/uvm_recorder.lo CXX print/uvm_printer.lo CXX print/uvm_printer_globals.lo CXX print/uvm_table_printer.lo CXX print/uvm_tree_printer.lo CXX reg/uvm_mem.lo CXX reg/uvm_mem_mam.lo CXX reg/uvm_mem_region.lo CXX reg/uvm_reg.lo CXX reg/uvm_reg_adapter.lo CXX reg/uvm_reg_backdoor.lo CXX reg/uvm_reg_block.lo CXX reg/uvm_reg_field.lo CXX reg/uvm_reg_fifo.lo CXX reg/uvm_reg_file.lo CXX reg/uvm_reg_indirect_data.lo CXX reg/uvm_reg_indirect_ftdr_seq.lo CXX reg/uvm_reg_item.lo CXX reg/uvm_reg_map.lo CXX reg/uvm_reg_model.lo CXX reg/uvm_reg_read_only_cbs.lo CXX reg/uvm_reg_tlm_adapter.lo CXX reg/uvm_reg_write_only_cbs.lo CXX reg/uvm_vreg.lo CXX reg/uvm_vreg_field.lo CXX reg/uvm_vreg_field_cbs.lo CXX report/uvm_default_report_server.lo CXX report/uvm_report_catcher.lo CXX report/uvm_report_catcher_data.lo CXX report/uvm_report_handler.lo CXX report/uvm_report_message.lo CXX report/uvm_report_object.lo CXX report/uvm_report_server.lo CXX seq/uvm_sequence_base.lo CXX seq/uvm_sequence_item.lo CXX seq/uvm_sequencer_base.lo CXXLD libuvm-systemc.la libtool: warning: library '/nis/asic/apps2/linux/sw/verilog/xcelium/XLM_20.09.011/tools.lnx86/cdsgcc/gcc/6.3/install/lib/../lib64/libstdc++.la' was moved. gmake[4]: Leaving directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/src/uvmsc' gmake[3]: Leaving directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/src/uvmsc' Making all in . gmake[3]: Entering directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/src' gmake[3]: Warning: File `uvmsc/libuvm-systemc.la' has modification time 0.031 s in the future CXXLD libuvm-systemc.la libtool: error: cannot find the library '/glad/common/pkgsData/gcc-v6.3.0p3/Linux/RHEL6.0-2013-x86_64/lib/../lib64/libstdc++.la' or unhandled argument '/glad/common/pkgsData/gcc-v6.3.0p3/Linux/RHEL6.0-2013-x86_64/lib/../lib64/libstdc++.la' gmake[3]: *** [libuvm-systemc.la] Error 1 gmake[3]: Leaving directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/src' gmake[2]: *** [all-recursive] Error 1 gmake[2]: Leaving directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/src' gmake[1]: *** [all] Error 2 gmake[1]: Leaving directory `/users/ricardga/Downloads/uvm-systemc-1.0-beta3/objdir/src' gmake: *** [all-recursive] Error 1 Sure enough that library/path in the error doesn't exist. But I don't know how to resolve the issue. Anyone have any ideas? Thank you,
  5. Hello Everyone, Could anyone please let me know what is the difference between Axi and TLM2.0. Which one is better, and where we can use both. Thanks
  6. //Question: i am using a inititator BFm to trigger as you can see and i am binding in sc_main but i sm getting error as discribed in the title, any suggestion ? SC_MODULE( initiator_bfm) { SC_HAS_PROCESS( initiator_bfm ); public: typedef vcn_lcm::initiator_bfm<AWIDTH, DWIDTH> this_int; sc_core::sc_in< bool > clk; sc_core::sc_in< bool > rst; sc_out< bool > wr_snd; initiator_bfm(sc_core::sc_module_name name_, if_int* pins_) : sc_core::sc_module(name_), pins(pins_), clk("clk"), rst("rst"), wr_snd("wr_snd") {} void run() { SC_CTHREAD(write_req , clk.pos() ); SC_CTHREAD(read_req , clk.pos() ); } void write_req(sc_dt::sc_uint<10> wr_addr_y, sc_dt::sc_uint<10> wr_addr_x, sc_dt::sc_uint<3> wr_num_qwords, sc_dt::sc_uint<7> wr_buff_id, sc_dt::sc_uint<16> wr_subbuf_id, sc_dt::sc_uint<2> wr_lcm_num, sc_dt::sc_biguint<320> wr_data ) { wr_snd.write(0); wait(); wr_snd.write(1); this->wr_addr_y.write(wr_addr_y); } } int sc_main(int, char*[]) { typedef vcn_lcm::vcn_lcm_if<10,320> vcn_lcm_if_t; typedef vcn_lcm::initiator_bfm<10,320> vcn_lcm_initiator_t; vcn_lcm_if_t* vcn_lcm_bus; vcn_lcm_initiator_t* vcn_lcm_init_bfm; vcn_lcm_bus = new vcn_lcm_if_t("vcn_lcm_bus"); vcn_lcm_init_bfm = new vcn_lcm_initiator_t("vcn_lcm_init_bfm",vcn_lcm_bus ); vcn_lcm_init_bfm->write_req(1,1,2,1,1,1,5); sc_signal< bool > wr_snd; vcn_lcm_bus->wr_snd(wr_snd); vcn_lcm_init_bfm->wr_snd(wr_snd); sc_start(100, SC_SEC); return 0; }
  7. Hello Everyone, I was trying to implement FSM in SystemC using SC_METHOD and next_trigger(). In the requirement it is mentioned i can't use SC_THREAD and static sensitivity (except reset_input). I am facing one problem here, which mentioned in screen-shot. In the attached screen-shot, whenever the current_state is FIRST then next_state could be SECOND, THIRED, and FOURTH (the priority of next_state is SECOND > THIRED > FOURTH). I am able to write a code using next_trigger when next_state is only one and not many. Here is the raw code: sc_in<bool> Reset_in; sc_in<bool> First_in ; sc_in<bool> Common_in; sc_in<bool> Second_in; sc_in<bool> Third_In; sc_in<bool> Fourth_in; SC_METHOD(FSMMethod) sensitive << Reset_in; async_reset_signal_is(Reset_in, false); dont_initialize(); void FSMMethod() { if (Reset_in == false) { current_state = RESET; next_trigger(); } else { switch (current_state) { case RESET: next_state = FIRST; next_trigger(First_in.posedge_event()); // now you can see when FSM is in RESET state then if First_in signal value become one //then FSM method will call again due to next_trigger and that time the next_state would be FIRST. break; case FIRST: // I am stuck here, if Common_in and Second_in signal true then next_state should be SECOND but the problem // is during the execution it will go inside the if block, if block not executed then next_trigger condtion // will not trigger the sc_method again and FSM will not in next_state. if (Common_in && Second_in) { next_state = SECOND; next_trigger(Common_in.value_changed_event() & Second_in.value_changed_event()); } else if (Common_in && Third_in) { next_state = THIRD; next_trigger(Common_in.value_changed_event() & Third_in.value_changed_event()); } else if (Common_in && Fourth_in) { next_state = FOURTH; next_trigger(Common_in.value_changed_event() & Fourth_in.value_changed_event()); } break } current_state = next_state; } } Hope i am able to put my question but if you guys need more clarification then please let me know. ultimatly i am not able to call FSMMethod beacuse next_trigger not executed in FIRST state, first we to have evalaute the transition condition then only next_trigger will execute. if in FIRST state if next_state were only one then it would be easy to use next_trigger (just in case we used in RESET to FIEST state) Please give me your valauble suggestions so it help to implement this FSM design. Thanks and Regards, ARI
  8. I am trying to design a GCD chip in SystemC using the model in the image. However, I have eliminated the subtractor and the comparator, and insert an ALU instead to have both functionalities in one module. I did not use the EOC either. Here is my code : #include <systemc.h> #include <ctime> class Register : public sc_module { public: sc_in<sc_logic> clk, reset, enable; sc_in<int> reg_in; sc_out <int> reg_out; SC_HAS_PROCESS(Register); Register(sc_module_name) { SC_METHOD(registering); sensitive << clk << reset; } void registering() { if (reset == '1') reg_out = 0; else if (clk->event() && (clk == '1')) if (enable == '1') reg_out = reg_in; } }; class Multiplexer: public sc_module { public: sc_in<int> in1, in2; sc_in<sc_logic> sel; sc_out <int> Out; SC_CTOR(Multiplexer) { SC_METHOD(muxing); sensitive << in1 << in2 << sel; } void muxing() { Out = (sel == '0') ? in1 : in2; } }; class ALU : public sc_module { public: sc_in <int> in1{ "in1" }, in2{ "in2" }; sc_out <int> out_sub{ "out_sub" }; sc_in < sc_logic > Opmode{ "Opmode" }; sc_out <sc_logic> equal{ "equal" }, greater{ "greater" }; SC_CTOR(ALU) { SC_METHOD(subtract); sensitive << in1 << in2; SC_METHOD(compare); sensitive << in1 << in2; } void subtract() { out_sub = 0; if (Opmode == '0') out_sub = in1 - in2; } void compare() { if (Opmode == '1') { if (in1 == in2) equal = SC_LOGIC_1; else if (in1 > in2) greater = SC_LOGIC_1; else greater = SC_LOGIC_0; } } }; class DataPath: public sc_module { public: sc_in <int> A{ "A" }, B { "B" }; sc_in <sc_logic> clk{ "clk" }, reset{"reset"}; sc_in <sc_logic> a_sel{ "a_sel" }, b_sel{ "b_sel" }; sc_in <sc_logic> ld_a{ "ld_a" }, ld_b{ "ld_b" }, ld_GCD{ "ld_b" }, OP_mode{"OP_mode"}; sc_in<sc_logic> sel_in1{ "sel_in1" }, sel_in2{"sel_in2"}; sc_out <int> GCD{"GCD"}; sc_out <sc_logic> AEB{ "AEB" }, AGB{"AGB"}; // A equal to B, A greater to B sc_signal<int> alu_in1{ "alu_in1" }, alu_in2{ "alu_in2" }, alu_out{"alu_out"}; sc_signal<int> regA_in{ "regA_in" }, regA_out{"regA_out"}; sc_signal<int> regB_in{ "regB_in" }, regB_out{"regB_out"}; sc_signal<sc_logic> regA_enb{ "regA_enb" }, regB_enb{ "regA_enb" }, regGCD_enb{"regGCD_enb"}; Multiplexer *muxA, *muxB, *muxRA, *muxRB; Register *RA, *RB, *RGCD; ALU *alu; SC_CTOR(DataPath) { muxA = new Multiplexer("muxA"); muxA->in1(A); muxA->in2(alu_out); muxA->sel(a_sel); muxA->Out(regA_in); muxB = new Multiplexer("muxB"); muxB->in1(B); muxB->in2(alu_out); muxB->sel(b_sel); muxB->Out(regB_in); RA = new Register("RA"); RA->clk(clk); RA->enable(regA_enb); RA->reset(reset); RA->reg_in(regA_in); RA->reg_out(regA_out); RB = new Register("RB"); RB->clk(clk); RB->enable(regB_enb); RB->reset(reset); RB->reg_in(regB_in); RB->reg_out(regB_out); muxRA = new Multiplexer("muxRA"); muxRA->in1(regA_out); muxRA->in2(regB_out); muxRA->sel(sel_in1); muxRA->Out(alu_in1); muxRB = new Multiplexer("muxRB"); muxRB->in1(regA_out); muxRB->in2(regB_out); muxRB->sel(sel_in2); muxRB->Out(alu_in2); alu = new ALU("alu"); alu->in1(alu_in1); alu->in2(alu_in2); alu->out_sub(alu_out); alu->equal(AEB); alu->greater(AGB); alu->Opmode(OP_mode); RGCD = new Register("RGCD"); RGCD->clk(clk); RGCD->enable(regGCD_enb); RGCD->reset(reset); RGCD->reg_in(B); RGCD->reg_out(GCD); /*SC_METHOD(datapath_function); sensitive << reset << a_sel << b_sel << sel_in1 << sel_in2 << ld_a << ld_b << ld_GCD;*/ } /*void datapath_function() { regA_in = (a_sel->read() == '0') ? A.read() : alu_out.read(); regB_in = (b_sel->read() == '0') ? B.read() : alu_out.read(); regA_out = (regA_enb.read() == '1' && ld_a.read() == '1') ? regA_in : regA_out; regB_out = (regB_enb.read() == '1' && ld_b.read() == '1') ? regB_in : regB_out; alu_in1 = (sel_in1->read() == '0') ? regA_out: regB_out; alu_in2 = (sel_in2->read() == '0') ? regA_out : regB_out; if (OP_mode->read() == "0") alu->subtract(); else alu->compare(); }*/ }; class Controller : public sc_module { public: sc_in <sc_logic> start{ "start" }, clk{ "clk" }, rst{ "rst" }, AEB{ "AEB" }, AGB{"AGB"}; sc_out <sc_logic> a_sel{"a_sel"}, b_sel{ "b_sel" }, ld_a{ "ld_a" }, ld_b{ "ld_b" }, ld_GCD{ "ld_GCD" }, OP_mode{ "OP_mode" }; sc_out<sc_logic> sel_ALU_in1{ "sel_ALU_in1" }, sel_ALU_in2{"sel_ALU_in2"}; enum states {idle, compare}; sc_signal <states> P_state{ "P_state" }, N_state{"N_state"}; // present and next states SC_CTOR(Controller) { SC_METHOD(next_state_gen); sensitive << start << P_state; SC_THREAD(seq_function); sensitive << clk << rst; } void next_state_gen(); void seq_function() { while(1) { if (rst == '1') P_state = idle; else if (clk->event() && (clk == '1')) P_state = N_state; wait(); } } }; void Controller::next_state_gen() { switch (P_state) { case idle: a_sel = SC_LOGIC_0, b_sel = SC_LOGIC_0, ld_a = SC_LOGIC_0, ld_b = SC_LOGIC_0, ld_GCD = SC_LOGIC_0; if (start == SC_LOGIC_1) { ld_a = SC_LOGIC_1, ld_b = SC_LOGIC_1; N_state = compare; } else N_state = P_state; break; case compare: sel_ALU_in1 = SC_LOGIC_0; sel_ALU_in2 = SC_LOGIC_1; OP_mode = SC_LOGIC_1; if (AEB == SC_LOGIC_1) { ld_GCD = SC_LOGIC_1; N_state = idle; } else if(AGB == SC_LOGIC_1) { OP_mode = SC_LOGIC_1; a_sel = SC_LOGIC_1; N_state = P_state; } else { sel_ALU_in1 = SC_LOGIC_1; sel_ALU_in2 = SC_LOGIC_0; OP_mode = SC_LOGIC_1; b_sel = SC_LOGIC_1; N_state = P_state; } break; default: N_state = idle; break; } } class GCD_ASIC : public sc_module { public: sc_in <sc_logic> clk{ "clk" }, rst{ "rst" }, start{"start"}; sc_in <int> A{"A"}, B{ "B" }; sc_out <int> GCD{"GCD"}; sc_signal <sc_logic> selA{ "selA" }, selB{ "selB" }; sc_signal <sc_logic> ALUsel_1{ "ALUsel_1" }, ALUsel_2{"ALUsel_2"}; sc_signal <sc_logic> LdRA{ "LdRA" }, LdRB{ "LdRB" }, LdGCD{ "LdGCD" }, OP_Sel{"OP_Sel"}; sc_signal <sc_logic> AEB{ "AEB" }, AGB{"AGB"}; SC_CTOR(GCD_ASIC) { DP = new DataPath("DataPath"); DP->clk(clk); DP->A(A); DP->B(B); DP->reset(rst); DP->a_sel(selA); DP->b_sel(selB); DP->ld_a(LdRA); DP->ld_b(LdRB); DP->sel_in1(ALUsel_1); DP->sel_in2(ALUsel_2); DP->OP_mode(OP_Sel); DP->AEB(AEB); DP->AGB(AGB); DP->ld_GCD(LdGCD); DP->GCD(GCD); CR = new Controller("Controller"); CR->clk(clk); CR->start(start); CR->rst(rst); CR->a_sel(selA); CR->b_sel(selB); CR->ld_a(LdRA); CR->ld_b(LdRB); CR->OP_mode(OP_Sel); CR->AEB(AEB); CR->AGB(AGB); CR->ld_GCD(LdGCD); CR->sel_ALU_in1(ALUsel_1); CR->sel_ALU_in2(ALUsel_2); } protected: DataPath *DP; Controller *CR; }; class GCD_ASIC_TB : public sc_module { public: sc_signal <sc_logic> clk, rst, start; sc_signal <int> A, B; sc_signal <int> GCD; GCD_ASIC *DUT; SC_CTOR(GCD_ASIC_TB) { DUT = new GCD_ASIC("DESIGN_UNDER_TEST"); DUT->clk(clk); DUT->rst(rst); DUT->start(start); DUT->A(A); DUT->B(B); DUT->GCD(GCD); SC_THREAD(clocking); SC_THREAD(reseting); SC_THREAD(inputing); } void clocking(); void reseting(); void inputing(); }; void GCD_ASIC_TB:: clocking() { while (true) { wait(10, SC_NS); clk = SC_LOGIC_0; wait(10, SC_NS); clk = SC_LOGIC_1; } } void GCD_ASIC_TB::reseting() { while (true) { wait(12, SC_NS); rst = SC_LOGIC_0; wait(15, SC_NS); rst = SC_LOGIC_1; wait(32, SC_NS); rst = SC_LOGIC_0; wait(); } } void GCD_ASIC_TB::inputing() { wait(2, SC_NS); start = SC_LOGIC_0; wait(20, SC_NS); start = SC_LOGIC_1; wait(20, SC_NS); //wait(); while (true) { srand(time(0)); wait(7, SC_NS); A = (int)(rand() % 256 + 1); srand(time(0)); wait(5, SC_NS); B = (int)(rand() % 256 + 1); } } int sc_main(int argc, char* argv[]) { GCD_ASIC_TB TB ("test_bench"); sc_trace_file *vcd_file; vcd_file = sc_create_vcd_trace_file("GCD_TEST"); sc_trace(vcd_file, TB.clk, "clock"); sc_trace(vcd_file, TB.rst, "reset"); sc_trace(vcd_file, TB.start, "start"); sc_trace(vcd_file, TB.A, "A"); sc_trace(vcd_file, TB.B, "B"); sc_trace(vcd_file, TB.GCD, "GCD"); sc_start(12000, SC_NS); sc_close_vcd_trace_file(vcd_file); return 0; } The problem is does not work. Could you please tell me where I am doing wrong?
  9. Hello, Assuming cycle accuracy is not needed, Is it possible to model external interfaces such as PIPE using standard TLM interfaces? If so, how do I take care of addressing in TLM interface to model an external interface that is not memory-mapped. Any suggestion is appreciated. Thank you.
  10. After the SystemC Evolution Fika panel discussion on Model Libraries, the Accellera SystemC Common Practices Subgroup has announced a call for contributions. We would appreciate contributions to collect industry best practices on modelling registers in SystemC. Our preference would be to receive a prototype (though it does not have to be 'complete') and it should also be useful to the SystemC CCI Working Group as an example implementation of a register that can be used to define a Register-discovery/Inspection API. If you or your organization has a way to model registers that you would like to share with the rest of the community, then we would like to hear from you. The call for contributions began on July 2 and will remain open until the end of August 2021. We will gladly take contributions of any form, as long as it complies with the Accellera IP Rights Policy. It would also help if you can give us an indication as soon as possible that you or your organization would like to contribute. For more information or to send a contribution, please contact the SystemC Common Practices sub working group chair: mark.burton@greensocs.com
  11. I am trying to model an OR gate with 2 NS output delay in SystemC. #include "systemc.h" SC_MODULE(adder) { sc_in<bool> A, B; sc_out<bool> OUT; void add() { while (true){ wait(A.default_event() | B.default_event()); bool intermediate = A.read() | B.read(); wait(2, SC_NS); //cout << "adding at time " << sc_time_stamp() << endl; OUT.write(intermediate); } } SC_CTOR(adder){ SC_THREAD(add); sensitive<< A << B;; } }; This is my attempt so far. But the simulation result is not as required: Time A B OUT 0 s 0 0 0 5 ns 1 0 0 6 ns 0 0 0 7 ns 0 0 1 13 ns 0 1 1 Instead of being 0 at 8 NS, it has missed the event at 6 NS. In Verilog, the events is similarly missed if blocking assignment is used. In Verilog, we fix it using non-blocking assignment (See this about Verilog: https://electronics.stackexchange.com/q/572643/238188). So how do I stop the event from getting missed in SystemC?
  12. Hi, I recently experienced an issue related to the static sc_vpool objects used in some classes in the SystemC kernel. Here is an example: #include <systemc.h> class Dummy { public: Dummy(int a) { sc_int<32> my_int(a); my_int(2,1); } }; Dummy dummy(12); int sc_main(int argc , char *argv[]) { return 0; } This program crashes at startup with the following stack trace: #0 0x0000000000404e66 in sc_dt::sc_int_subref_r::initialize (this=0x0, obj_p=0x7fffffffdde0, left_i=2, right_i=1) at /remote/vgrnd104/julient/OSCI/linux/systemc-2.3.3/include/sysc/datatypes/int/sc_int_base.h:338 #1 0x0000000000405102 in sc_dt::sc_int_base::operator() (this=0x7fffffffdde0, left=2, right=1) at /remote/vgrnd104/julient/OSCI/linux/systemc-2.3.3/include/sysc/datatypes/int/sc_int_base.h:1282 #2 0x000000000040513f in Dummy::Dummy (this=0x701b11 <dummy>, a=12) at test.cpp:7 #3 0x0000000000404d81 in __static_initialization_and_destruction_0 (__initialize_p=1, __priority=65535) at test.cpp:11 #4 0x0000000000404d97 in _GLOBAL__sub_I_dummy () at test.cpp:15 #5 0x00000000004c623d in __libc_csu_init () #6 0x00007ffff702ecb0 in __libc_start_main () from /lib64/libc.so.6 #7 0x0000000000404c29 in _start () Note that the example only crashes when it is statically linked to the SystemC library. It does not crash when it is dynamically linked to the SystemC library. This crash is caused by a wrong order of initialization of the static and global objects: - The dummy global variable is initialized first. - The constructor of Dummy calls sc_int_base::operator() which uses the static sc_int_subref::m_pool object (sc_int_base.h line 1281). - But m_pool has not yet been created. This leads to the crash. So this crash is a typical static initialization order fiasco situation. However, the above example is very simple and does nothing uncommon. And the crash is related to an internal implementation of the SystemC kernel. So it is very hard for the SystemC user to understand why his program crashes and why he should change his code to make it work. So I would suggest to change the internal implementation to avoid using static sc_vpool objects. Current implementation: sc_int_base.h line 527: static sc_core::sc_vpool<sc_int_subref> m_pool; sc_int_base.h line 1281: sc_int_subref* result_p = sc_int_subref::m_pool.allocate(); Maybe I'm missing something, but the following might be a possible new implementation: sc_int_base.h line 527: static sc_core::sc_vpool<sc_int_subref>& pool() { static sc_core::sc_vpool<sc_int_subref> subref_pool; return subref_pool; } sc_int_base.h line 1281: sc_int_subref* result_p = sc_int_subref::pool().allocate(); Similar changes should be done for all the static sc_vpool objects. Thus, static sc_vpool objects would not be necessary anymore, and this would avoid this crash. Any opinion about that? Thanks. Julien
  13. Hi all, I was trying something different and came across a issue which looks odd to me. I have a main function and from there I am calling sc_main(). In sc_main, I am starting and ending simulation < sc_start, sc_stop >. something like Example : int main(){ sc_main() //gives the expected output sc_main() // creashes Error: insert module failed: elaboration done return 0 } I am expecting that my simulation should run 2 times. But, I am facing " ERROR- insert module failed: elaboration done " while calling 2nd sc_main. ---Its seems like the old simulation is itself not getting cleared---- As after doing sc_stop the simulation should stops and clears all memories, then I believe it should have worked. --Can any help me to make this done, if possible-- Any hint will be very helpful for me. Thanks in advance :). Best Regards, Nitin
  14. Is there a way to identify each generic payload transactions with id? I need some id that I can print out as my transaction flows from initiator to target via different modules. Thanks
  15. Hello friend, I am super beginner. I am trying to run this example code http://www.asic-world.com/systemc/first1.html#Counter_Design_Specs counter design and counter testbench on my systemc with visual studio. So I got two error. Here I put the error together. Severity Code Description Project File Line Suppression State Error (active) E0304 no instance of overloaded function "sc_start" matches the argument list Project1 C:\Users\60182\source\repos\Project1\Project1\first_counter_tb.cpp 17 Severity Code Description Project File Line Suppression State Error C2665 'sc_core::sc_start': none of the 4 overloads could convert all the argument types Project1 c:\users\60182\source\repos\project1\project1\first_counter_tb.cpp 17
  16. Hello all, This is very basic question and I know its not possible, but still I need to put some delay or wait in start of simulation/end of elaboration. I will give you the background, In end of elaboration i an initializing the value to a pin, and that pin is quite required for reset vector address. In start of simulation I am opening my gdb, which which stop at my reset vector address, but it seems the gdb is not updating the reset vector value, so I need a small delay. Is it possible? Any suggestion will be very helpful :) Thanks and Regards, Nitin_s
  17. I am trying to model a direct mapped cache and there is main memory module which is an SC_CTHREAD and main memory state machine which also SC_CTHREAD. I am experiencing one clock cycle delay when I write to an output from main memory and read it from main memory state machine. But i thought i could read in the same clock cycle isnt it true?
  18. I have a module which shapes the data and then dump into the memory module depending on if data input is more than Bandwidth. If data input is less than Bandwidth then it will bypass it that means no clock cycle wastage and the way to bypass is only if I can call the process of memory module from shaper module for writing the data. So, is it possible to do what I am thinking? or I can do the bypassing without calling the process of memory module?
  19. Hi, I am trying to model large memories (>8 GB) on a virtual platform that I am working on. I don't think using the C++ 'new' operator to allocate the entire chunk is a good idea. Can someone suggest any methods they think or have used in the past to model such? My memory is going to be very sparse to start with and might start filling up only at a later time. Thanks,
  20. Hi, I wanted to know ,is it possible to trace waveforms in tlm.I tried for alternate ways as it was done in system c earlier also.But i wasnt successful in my attempts. One of the way i tried was by using the init_socket and targ_socket again in top which is completely wrong i guess.I cant reuse the tlm sockets again for my instantiated modules. int sc_main(int argc,char* argv[]) { initiator* init; target* targ; tlm_utils::simple_initiator_socket<initiator>i_top_socket; tlm_utils::simple_initiator_socket<target>t_top_socket; init = new initiator("init"); targ = new target("targ"); init->i_socket(i_top_socket); targ->t_socket(t_top_socket); sc_clock clk1("clk1", 10, SC_NS, 0.5); sc_clock clk2("i_t_clk", 20, SC_NS, 0.5); init->i_socket.bind(targ->t_socket); init->ext_i_clk(clk1); targ->int_t_clk(clk2); sc_trace_file* tf = sc_create_vcd_trace_file("b_transport"); sc_trace(tf, clk1, "ext_clk"); sc_trace(tf, clk2, "t_clk_internal"); sc_trace(tf, init->i_socket, "i_socket"); sc_trace(tf, targ->t_socket, "i_socket"); sc_start(200, SC_NS); sc_close_vcd_trace_file(tf); return 0; } The other way i tried was getting the arguments not matching error i.e arguments support sc_signal type and i am using tlm types.I kno that the compiler is telling the difference in arguments,but whats the alternate solution for this problem ? Can anyone please tellme where am i going wrong and how to trace the transaction exactly ? And Is it really possible to trace waveform in tlm ? Thanks & regards, Shubham
  21. I have recently started using SystemC for my project. I would appreciate if someone could help me with following problem. How can I select part of input port in SystemC? In Verilog it can be done easily by choosing the required bits, e.g., inputPort[3:1] How can I do this in Systemc? I have defined an input port as follows sc_in < sc_int<5> > inputPort; What is the syntax to read bits e.g., [1:3] from inputPort like I did in Verilog? I tried few syntax like inputPort.read({1:3}) but no success.
  22. Hi, I have declared and defined the clock in my example and able to generate and transport the transactions successfullly. As its is a blocking transport interface of tlm,so we are using wait statement. But what i observed here is, i am not able to control the triggering of process by using clocks for both the modules.Thiugh , i am able to controll the thread awakening by using delay statements. What if i want to use clocks to controll the trigger ,thats why i had put them in the sensitivity list. Please let me know,what would be my approach for the triggering by clocks.? do i need to look out for other interface method in tlm or should i go back to system c interface approach ? Please help me out with this. Thanks & regards, Shubham Ps:- I am attaching the code along with the block diagram below,please let me know the solution for it.The block diagram represents 2 blocks of initiator and target modules with clock supplied. Iam able to compile and run the code succesfully,if you get any error while compiling i might have done mistake while copying. initiator.h.txt main.cpp.txt target.h.txt initiator2.h.txt target2.h.txt top.h.txt
  23. Dear all, I need to do floating point arithmetic in systemc. My question is if after I do two floating point addition or multiplication, can I call this api(is_inf()) for the sum or product to determine it is inf or not? The produced results looks correct for me. Like the following sample code ```c num1.negative(sign1); num2.negative(sign2); num1.exponent(exp1); num2.exponent(exp2); num1.mantissa(significand1); num2.mantissa(significand2); //the additiion result result = num1+num2; cout.precision(23); cout << result.is_inf() << " " << num1 << " " << num2 << " " << result << endl; ``` The following are my test samples: The first column is is_inf flag, the second and the third column are the source operands and the last column is the produced result. ``` 1 -3.402823466385288598117e+38 -3.402823466385288598117e+38 -inf 0 0.5 -0.20000000298023223876953 0.30000001192092895507812 0 0.5 -9.9999997473787516355515e-05 0.49990001320838928222656 0 0.5 -0.30000001192092895507812 0.19999998807907104492188 0 0.5 100 100.5 0 0.5 2003 2003.5 0 0.5 100000 100000.5 0 0.5 -1000000 -999999.5 ``` Any guidance is appreciate.
  24. Hi, I was having few questions regarding clock usage in tlm.These are as folllows:- 1.I wanted to know whether we can supply clock to initiator and target modules. 2.If it can be used ,then how to do we need need to connect to modules.Like instantiate clock in top module and how should we do port or named mapping ? If not,then why its not used ? Because i havent come across any examples in tlm which uses clocks. 3.If we are using blocking interface then using wait statement,just that data doesnot get overidden. And if its a case of nb_interface then we are using delay statements . My question here would be,can i create system clock input port and connect them ? I had tried but i had got a failed port mapping error message. Thanks & regards, Shubham
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