Jump to content

Search the Community

Showing results for tags 'phase'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM (IEEE 1800.2) - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
  • Portable Stimulus
    • Portable Stimulus Discussion
    • Portable Stimulus 2.0 Public Review Feedback
  • IP Security
    • IP Security Assurance Whitepaper Discussion
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests


Biography


Location


Interests


Occupation


Company

Found 7 results

  1. Hi why does phase.find_by_name(.name(uvm_main_phase::get().get_name()), .stay_in_scope(0)); from run_phase and uvm_pkg::uvm_phase run_phase = phase.find_by_name(.name(uvm_run_phase::get().get_name()), .stay_in_scope(0)); from main_phase return null. Is this intentional? I have created a sample example to check, or you can use the attached file as well. https://www.edaplayground.com/x/5Py7 test.svh
  2. Hi, I have a doubt about requirement of raise/drop_objection. Why does a compiler need objections in run_phase? Why can it not just wait for time given like 100ns as following example? Ex. task run_phase(uvm_phase phase); //phase.raise_objection(this); #100ns; //phase.drop_objection(this); endtask
  3. Hi, As per my understanding, connect_phase does not start until all build_phase do not complete. How is this mechanism controlled? I did not find anything in uvm reference manual about this. Please let me know if there is any. Thanks.
  4. T or F: Objections should not be used in the uvm phases which are functions (i.e. build_phase, connect_phase, check_phase, ...). If True, why?
  5. In our testbench , we have added a new schedule pcie_main_schedule which runs in parallel with uvm_main_phase. This schedule consists of four phase lets say phase_a , phase_b , phase_c and phase_d. So the flow looks as shown below: pre_reset_phase | | <Other run time phase > | | Main_phase | phase_a | | | | | phase_b | | | | | phase_c | | | | |
  6. In our testbench , we have added a new schedule which runs in parallel with uvm_main_phase. This schedule consists of four phase lets say phase a , b , c and d. These phases are added into uvm domain(m_uvm_domain) itself. So the flow looks as shown below: pre_reset_phase | | <Other run time phase > | | Main_phase | phase_a | | | | | phase_b | | | | | phase_c | | |
  7. Hello, I was wondering if anyone had any ideas on why my test is hanging at the end of the run phase and how to resolve it correctly. The last of the output is listed below. The testbench has a series of agents, each including a monitor, producer driver, consumer driver, and scoreboard. At the end of the run phase when the test is hanging I'm able to step through code and see it's executing in a forever loop in the monitor and consumer driver. In both of these I'm never raising any objection. Tracing through the UVM code it seems it's waiting for all threads to exit before moving on. Som
×
×
  • Create New...