controlled transition from one phase to another

[anshulgarg]

Hi,

 

As per my understanding, connect_phase does not start until all build_phase do not complete.

 

How is this mechanism controlled?

 

I did not find anything in uvm reference manual about this.

Please let me know if there is any.

 

Thanks.

[tudor.timi]

Do you need to know exactly how an engine works to be able to drive a car? The whole point of using libraries is that you don't need to care how they're implemented, rather how to use them. Coming back to the car analogy, the UVM user guide isn't a service manual, so it won't describe the parts the car is made of and how they're connected. It will tell you what buttons to press to turn on the radio, to turn on the AC, start the engine, etc.

[anshulgarg]

I agree with you, but there is no problem in understanding how car engine work also. I had a doubt, I asked people where to ask, they suggested this site. And I think if somebody just want to learn, you cant just stop him. Coming back to car analogy, there are lot of posts you can see about how a car engine works.
If you know the answer, please let me know.
 

Thanks.

[tudor.timi]

I guess for this you're going to have to open the hood and have a look (into the BCL source code).

[bhunter1972]

Here's a high-level overview:

 

When the build phase starts, the test component is created and its build phase is run.

As the test creates more components, each component registers with the UVM environment and is added to a list of components whose build phases haven't run yet.

When the test's build phase is complete, UVM then goes through the list of components and runs their build phases. Each, in turn, may add more sub components to the list.

Wash, rinse, repeat.

When the list is empty, then all components have run through their build phases and the UVM build phase is complete.

 

Same thing happens with the connect phase and all the rest, except that in those no more components will be added.

 

 

So, you see, it's just like a car.